3rd 3DDRESD: ReCPU 4 NIDS

Regular Expression Matching for NIDS Computation [email_address] 3d DRESD 2008

Rationale and objectives ,[object Object],[object Object],[object Object]

Presentation Outline ,[object Object],[object Object],[object Object],[object Object]

What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Pattern matching: State of the art ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Limitations ,[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Proposed Approach: ReCPU ,[object Object],[object Object],[object Object],[object Object],[object Object]

ReCPU instructions 1/2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

ReCPU instructions 2/2 ,[object Object],[object Object],[object Object],[object Object]

Instruction format ,[object Object],[object Object],[object Object],[object Object],[object Object]

Bitwise representation of the opcodes

ReCPU test configuration ,[object Object]

Architecture description 1/5 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Architecture description 2/5 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Architecture description 3/5 ,[object Object],[object Object],[object Object],[object Object]

Architecture description 4/5 ,[object Object],[object Object],[object Object],[object Object],[object Object]

Architecture description 5/5 Each cluster is shifted of one character from the previous in order to cover a wider set of data in a single clock cycle.

example Comparator clusters working on an input text. The top and bottom pictures correspond to two subsequent clock cycles.

Data Path 1/2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Data Path 2/2 ,[object Object],[object Object],[object Object],[object Object],[object Object]

Control Path 2/2 ,[object Object]

Non matching state ,[object Object],[object Object],[object Object]

Matching state ,[object Object],[object Object],[object Object]

The complete Framework ,[object Object]

Adaptability of the design ,[object Object],[object Object],[object Object],[object Object]

The compiler ,[object Object],[object Object],[object Object],[object Object]

Design Space Exploration ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Design Space Exploration Results It is possible to identify the best architecture according to area and performance requirements

Performance ,[object Object],[object Object]

Experimental results ,[object Object],[object Object],[object Object]

NIDS overview 1/2 ,[object Object],[object Object],[object Object]

NIDS overview 2/2 ,[object Object],[object Object],[object Object],[object Object],[object Object]

Packet analisys ,[object Object],[object Object],[object Object],[object Object]

Snort ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object]

IP Fragmentation issues ,[object Object],[object Object],[object Object]

Implementing on Board ,[object Object],[object Object],ReCPU core IP CORE Ethernet MicroBlaze OPB bus

steps ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

3rd 3DDRESD: ReCPU 4 NIDS

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3rd 3DDRESD: ReCPU 4 NIDS