3D-DRESD Lorenzo Pavesi

Università Milano Bicocca Studio di Tecniche di compilazione parallela per architetture riconfigurabili Pavesi Lorenzo 071042

Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object]

Hybrid Processors ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

XiRisc+PiCoGa e GriffyC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

PGAop ,[object Object],[object Object],+ + + A B C D Y A B C D Y

GriffyC L1 : sub a,a,2 rol b,b,a add d,d,a add c,b,d add i,i,1 bnz c,L1 sub a,a,2 add d,d,a rol b,b,a add c,b,d add i,i,1 A D I B L1 : sub a,2 rol b,a add d,a add c,b,d add i,i,1 bnz c,L1 PGAop a,b,d,i [..] for(;c!=0;i++)[ a=a-2; b=b<<a; d=d+a; c=b+d; ] [..] [..] PD_0=pga_allocate(myPGAop); [..] for(;c!=0;i++)[ pgadirect1(PD_0, a,i,b,d); ] [..] pga_deallocate(myPGAop); [..]

SUIF ,[object Object],[object Object],[object Object],[object Object],[object Object],Suifdriver Pass - analyses - optimization IR - suifnodes - basicnodes Kernel - suifkernel - iokernel MODULES

Machine SUIF Optimization & Analysis Algorithms O P I Target Machines Compilation Environment ( SUIF ) ,[object Object],[object Object],[object Object],Suif (v.2.1) Machine SUIF-IR (qui è definito machine ir.hoof file) OPI cfa bvd suifvm x86 alpha cma / ssa picovm ksta ex1 m2gc Parametrized Target dependent Compilation Environment is defined Str.Anl machine cfg ssa

Flusso di compilazione per PiCoGA C to SUIF LIR MACHINE-SUIF CFG STRUCTURAL ANALYSIS KERNEL IDENTIFICATION ,[object Object],[object Object],[object Object],PiCoGa Kernel translation ,[object Object],[object Object],[object Object],[object Object],GRIFFY–C COMPILER ,[object Object],[object Object],KERNEL EXTRACTION 1 2 3

Generazione del GriffyC ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ C SUIF SUIF (LIR) Dismantling delle strutture di controllo FileSetBlock FileBlock procedure procedure procedure FileBlock procedure procedure Machine SUIF CFG

Generazione del GriffyC picovm Control Tree ANNOTED Mach – SUIF ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ PICOHEADER ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ FileSetBlock FileBlock procedure procedure procedure FileBlock procedure procedure kernel Ottimizzazioni sul tipo di selezione ottimizzazioni sul body del kernel Selezione 2 3 Ranking & Estrazione SSA M2GC ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ ...... ........ ......#ifndef PICOHEADER__provaTmp1 #define PICOHEADER__provaTmp1 #pragma fpga _provaTmp1 0x00 0 0 { /* Virtual register declarations */ void * _vr0; double _vr1; float _vr2; _vr4 = (float (*)[1])part_amplitude; _vr5 = (float *)_vr4; _vr6 = (float *)((char *)_vr5 + _vr3); _vr7 = *_vr6; _vr2 = (float)_vr7; _vr1 = (double)_vr2; printf(_vr0, i, _vr1); } #pragma end #endif /*PICOHEADER__provaTmp1*/ Structural Analysis 1 X

Test e Risultati ,[object Object],[object Object],Block division DCT Storage DCT Quantize Entropy Encoder IDCT Entropy Decoder Immagine Reconstruct Dequantize originale Immagine

Conclusioni ,[object Object],[object Object],[object Object],[object Object]

Sviluppi Futuri ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

3D-DRESD Lorenzo Pavesi

Empfohlen

Empfohlen

Weitere ähnliche Inhalte

Was ist angesagt?

Was ist angesagt? (20)

Andere mochten auch

Andere mochten auch (6)

Ähnlich wie 3D-DRESD Lorenzo Pavesi

Ähnlich wie 3D-DRESD Lorenzo Pavesi (20)

Mehr von Marco Santambrogio

Mehr von Marco Santambrogio (20)

Kürzlich hochgeladen

Kürzlich hochgeladen (20)

3D-DRESD Lorenzo Pavesi