RICHTOP Project Presentation

1. Methods for Fast Yield Learning in A DRAM Wafer Fab using a Remote Packaging and Test Site .

2. Authors

3. Abstract In this paper, we describe the issues and solutions for overcoming the distance between a DRAM wafer fab facility and a remote packaging and test site. Fast cycle time of experimental feedback allow for accelerated yield learning and volume ramping.

4. INFINEON - Richmond

5. INFINEON - Porto

7. SPECIAL REQUESTS SWR’s: (Special Work Requests) - FE (wafer Front End) lots with non-standard processing (examples: extended BI, DC Dataloging for Characterization) or experimental designs used to evaluate a potential yield improvement, performance window or new tool qualification. New Product or Technology introduction . - FE lots of a new product or technology which in development. A Front End Process excursion - Potential quality risk which requires non-standard processing and/or containment.

9. PROJECT MANAGEMENT The TEAM

10. PROJECT MANAGEMENT The Charter

11. PROJECT MANAGEMENT The PLAN

13. LOT LEVEL ATTRIBUTES The Porto WIP system was modified to read these attributes and run the lots thru newly created test flows as listed in Table.

16. RESULTS (Volume Assesment)

17. RESULTS (Daily Shipment Report)

18. RESULTS (Summary) Quality Gate and Lot Attributes Quality Gates & Engineering Intervention Risk Containment Lot Level Parameters in FAB300 SWR Document Special Lot Flows WEB Based Report PROMIS WIP Forecast (Fig.4) Wafer Level Lot Level Quality Assessment 5% 30% Volume Impact 2X ( Fig.3 ) 2X (theoretical) Cycle Time PORTO BE RICHMOND BE FEATURE

19. CONCLUSION Transfer and development of BE learning systems from Richmond to Porto provided an estimated annual savings of $30M with no change in the learning rate and yield ramp of the Richmond FE. The system is currently planned for transfer to other Infineon BE sites in Malacca and China.