Recosoc'11 presentation

1. FPGA
SDK
for
Nanoscale
Architectures
@
Ciprian.Teodorov
Loic.Lagadec
univ-­‐brest.fr
ReCoSoC’11
–
Montpellier,
21-­‐23
June
2011

2. Overview
• Emerging
Technologies
• Nanoscale
Architecture
Template
• FPGA
Tools
for
Nano
• Results
FPGA
SDK
for
Nanoscale
Architectures
2

3. Context
?
• CMOS
reaching
its
limits
– Physical
– Material
Emerging
– Power-­‐Termal
Technologies
– Technological
– Economical
FPGA
SDK
for
Nanoscale
Architectures
3

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Golstein
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I.
O’Connor
(INL)
CMOL,
K.
Likharev
Vdd
PC1 !"#$ !"#% !"#& '
EV1 PC2
EV1 !" !" !" $!%
Y
PC2 !" !" #" $!%
A VbA VbB B VbC
EV2 !" #" !" $&%
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J. Liu, I. O'Connor, D. Navarro, F. Gaffiot,
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El. Lett., 43(9), April 2007 #" #" !" $&%
! boolean data inputs A and B (logic levels
Nasic,
C.A.
Moritz
#" #" #" $&%
at Vss=0V and Vdd=1V) + circuit output Y
!" ( !" $
! four-phase non-overlappingFPNI,
HP,
G.S.
Snider
clock signals !" ( #" $
– two pre-charge inputs PC1, PC2
( !" !" %
– two evaluation inputs EV1, EV2
( !" #" %
! control inputs VbgA, VbgB, VbgC to configure
( ( ( '
circuit to 1 of 14 functions (back-gate bias
( ( #" (
-1V / p-type and +1V / n-type)
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QCA,
Notre
Dame
NanoCell,
J.
M.
Tour
NanoPLA,
A.
DeHon
FPGA
SDK
for
Nanoscale
Architectures
4

5. NASIC
Fabric
Principles
FPGA
SDK
for
Nanoscale
Architectures
5

6. Roung
Problem
FPGA
SDK
for
Nanoscale
Architectures
6

7. MultiNW-gated FET
CMOS-gated NWFET
CMOS I/O
Output
Input Logic
Connection
HeightCell
Routing Block
VDD
eva
pre
GND
WidthCell
FPGA
SDK
for
Nanoscale
Architectures
7

8. FPGA
SDK
for
Nanoscale
Architectures
8

9. R2D
NASIC
• Compability
with
the
NASIC
• Adaptability
to
a
variety
of
technological
and
applicave
constraints
• Compability
with
NASIC
fault-­‐tolerance
techniques
• Regularity
=>
custom
placement
and
roung
• Max-­‐rate
pipeline
designs
based
on
its
pipelined
roung
architecture
• Simplified
delay
esmaon,
due
to
the
dynamic
logic
evaluaon
and
pipelined
roung
architecture
FPGA
SDK
for
Nanoscale
Architectures
9

10. Tools
for
nano
PLAMap
–
PLA
VFLib
–
tech.
Proprietary
extracon
mapping
tools
&
algos
VPR
Madeo
NanoPLA
&
@
nanoscale
CMOL
FPGA
SDK
for
Nanoscale
Architectures
10

11. Madeo
FPGA
Toolkit
• Reconfigurable
architecture
&
generic
tools
– P&R,
allocaon,
circuit
edion
• High-­‐level
logic
compiler
– HLS
&
opmized
arithmecs
• System
and
architecture
modeling
(SoC)
– logic
primives,
processes
– hardware-­‐plagorm
management
– system
acvity.
FPGA
SDK
for
Nanoscale
Architectures
11

12. Madeo
at
Nanoscale
• Model
extensions:
– nanogrid,
nanowire
(crossbar
fabric
level)
– Turn
connecons,
and
PLAs
(R2D
Nasic)
• HDL
evoluon
for
nano
model
instanaon
• Algorithmic
extensions:
– Espresso
PLA
opmizaon
– Netlist
paroning
for
PLAs
– PLA
placement
– New
roung
algorithms
FPGA
SDK
for
Nanoscale
Architectures
12

13. R2D
NASIC
Design
Flow
SIS
PLA
Family
Exploraon
Architecture
PLAMap
MADEO
Metrics
Placement
Roung
Layout
FPGA
SDK
for
Nanoscale
Architectures
13

14. Results
–
Area
100
48.43X
24.06X
17.35X
10 12.05X
8.76X
2.18X
1.32X
1
alu4 apex2 apex4 des ex5p misex3 seq
FPGA
SDK
for
Nanoscale
Architectures
14

15. Speed
Operang
frequency
of
the
slowest
logic
stage
/
throughput
1000
167MHz
100
67MHz
Too
Frequency
43MHz
40MHz
slow
29MHz
27MHz
10
9MHz
1
alu4
apex2
apex4
des
ex5p
misex3
seq
Results
assume
1GHz
for
the
slowest
logic
stage
FPGA
SDK
for
Nanoscale
Architectures
15

16. Max-­‐Rate
Pipeline
System
Add
REs
FPGA
SDK
for
Nanoscale
Architectures
16

17. b a
c d
FPGA
SDK
for
Nanoscale
Architectures
17

18. Results
–
Speed
Net Performance Improvement
77.15X
32.58X 31X
24.21X 23.78X
10.56X
4.8X
alu4 apex2 apex4 des ex5p misex3 seq
FPGA
SDK
for
Nanoscale
Architectures
18

19. Results
–
Area
100 Normalized density advantage
48.43X over 45nm standard cell design
24.06X
17.35X
11.52X 12.76X 12.05X
10 8.76X
2.72X
2.18X
1.32X 1.24X
1
0.46X
0.1
0.06X
0.03X
0.01 alu4 apex2 apex4 des ex5p misex3 seq
FPGA
SDK
for
Nanoscale
Architectures
19

20. Performance*Area
1000
274X
100
66X
61X
40X
14X
10
5X
1
alu4
apex2
apex4
des
ex5p
misex3
seq
0,32X
0,1
FPGA
SDK
for
Nanoscale
Architectures
20

21. Room
for
Improvement
Std. dev. of misex3 switch-use map
switch ressource use 740
334
301
243 255
149
65 32
alu4 apex2 apex4 des ex5p misex3 seq AVG
FPGA
SDK
for
Nanoscale
Architectures
21

22. Conclusion
• Regular
nano
architecture
template
– Custom
placement
&
roung
• Incremental
DSE
with
MADEO
toolkit
• Future work:
– R2D
NASIC
wrt.
fault
tolerance
and
ming
issues
under
variability
assumpons.
– Improve
toolkit’s
extensibility
by
further
decoupling
the
tools
from
the
target
architecture
FPGA
SDK
for
Nanoscale
Architectures
22

23. Thanks
for
your
alenon!
Q&A
FPGA
SDK
for
Nanoscale
Architectures
23