1. Design of CMOS Sampling Switch for Ultra-Low Power ADCs
in Biomedical Applications
Dai Zhang, Ameya K Bhide and Atila Alvandpour
Division of Electronic Devices, Department of Electrical Engineering, Linköping University, Sweden
E-mail: {dai, ameya, atila}@isy.liu.se
Abstract - This paper deals with the design of CMOS
sampling switch for ultra-low power analog-to-digital
converters (ADC) in biomedical applications. General switch
design constraints are analyzed, among which the voltage
droop due to the subthreshold leakage current constitutes the
major error source for low-speed sampling circuits. Based on
the analyses, a CMOS sampling switch with leakage-
reduction has been designed for a 10-bit 1-kS/s successive
approximation (SA) ADC in a standard 130 nm CMOS
process. Post-layout simulation shows that the ADC with the
proposed switch offers an effective number of bits (ENOB) of
9.5 while consuming only 64 nW. Figure 1. (a) A basic sampling circuit (b) CMOS switch.
1. INTRODUCTION V s2 (V FS / 2 2 ) 2 V FS ⋅ C S
2
Ultra-low power ADCs are important components in SNR thermal = = = (1)
V n
2 kT / C S 8kT
biomedical applications such as implantable pacemakers,
The thermal noise leads to a trade-off between precision
where a long battery lifetime is needed to sustain the
and speed. In order to achieve a high SNR, the sampling
device for 10 to 12 years [1]. Since the bio-signals are
capacitance must be sufficiently large, thus degrading the
low-frequency by nature [2], an ADC with high operating
speed.
speed is not required.
Sampling is one of the key functions performed by
2.2. Sampling Time Jitter
ADCs. A basic sampling circuit consists of a switch and a
The uncertainties in the clock, together with the delay
hold capacitor, shown in Figure 1(a). The switch usually
between logic blocks that generate the sampling-signal,
consists of a CMOS transistor, shown in Figure 1(b),
determine jitter at the actual sampling instant. The error
which allows rail-to-rail swing and decreases overall on-
voltage introduced by the sampling time jitter depends on
resistance. During operation of the ADC, the sampling
both the clock jitter and the time derivative of the input
circuit may introduce various linear and nonlinear effects
signal [3]. The related SNR is:
which degrade the accuracy of ADC.
This paper will first address the general design SNR jitter = −20 log(2π ⋅ f IN ⋅ δ T ) (2)
constraints of the CMOS sampling switch. The analyses where fIN is the input frequency and δT is the clock jitter.
identify voltage droop due to subthreshold leakage current Equation (2) shows that the jitter could be a limiting factor
as the major error component in the sampling circuit when for large SNR and high frequency designs, while it can be
the sampling rate goes low. A leakage-reduced CMOS easily tolerated for low-speed circuits. For instance, the
switch is designed for a 10-bit SA ADC working at a jitter should be limited to 1 ps to achieve 84 dB SNR
sampling rate of 1 kS/s. In addition, all the design when sampling a 10 MHz sine wave. As the allowable
constraints of the switch are considered and their effects jitter and input frequency are inversely proportional, hence
are characterized. The proposed switch is ensured to meet a jitter of 1 ns can be tolerated to achieve the same SNR
the given specification of the SA ADC. Finally, the when sampling a 10 kHz sine wave.
performance of the whole ADC was simulated based on
post-layout extraction. 2.3. Switch-Induced Error
Charge injection and clock feedthrough, collectively
2. GENERAL DESIGN CONSTRAINTS OF CMOS known as the switch-induced error, are the major sources
SAMPLING CIRCUIT of error caused by the turning-off of the switch. Charge
2.1. Thermal Noise injection introduces error to the sampled voltage by
The thermal noise, introduced by the on-resistance of depositing part of the charge from the conduction channel
the switch, is given by kT/CS, where k is the Boltzmann of the transistor onto the sampling capacitor; clock
constant, T is the absolute temperature, and CS is the feedthrough affects the sampled voltage by capacitance
sampling capacitance. To quantify the effect of the noise, coupling during the transition of the sample signal. The
we assume that a sinusoidal signal with a full-scale range switch-induced error voltage for both NMOS and PMOS
of VFS is applied to the input of the switch, and the can be approximated as [4]:
consequent signal-to-noise ratio (SNR) is:
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2.  kWN LN COX (VDD − VTHN −VIN ) CGD, NMOS Table 1. Influence of design parameters on different error
− − VDD NMOS components
 CS CS + CGD, NMOS
∆Verr = (3)
 kWP LP COX (VIN − VTHP ) + CGD, PMOS V PMOS VIN CS VDD fS
 CS CS + CGD, PMOS
DD
 Thermal noise - -
Jitter - - -
where k is the fraction of charge injected on the output Bandwidth nonlinear
node, COX is the gate-oxide capacitor, VTHN and VTHP are Switch-induced error linear - -
the threshold voltages, and CGD,NMOS and CGD,PMOS are gate- Voltage droop nonlinear
drain overlap capacitance of NMOS and PMOS,
respectively. In Equation (3) for NMOS (respectively nonlinear dependence on the input-output voltage
PMOS), the first item represents the charge injection error, difference of the switch. This has been verified by
which varies with the input signal in a linear fashion if the simulation, as shown in Figure 2, for a standard CMOS
body effect is not considered, and the second item switch implemented in 130 nm CMOS with minimum size
represents the clock feedthrough error, which is input- and a P/N ratio of 4. The simulation result shows that the
signal independent. Both of these effects can be reduced leakage current grows exponentially with the increase of
by increasing the sampling capacitance. the input-output voltage difference of the switch.
Therefore, the leakage current introduces nonlinear errors
2.4. Tracking Bandwidth such as harmonic distortion to the ADC.
The sampling circuit forms a low-pass RC network,
with a tracking bandwidth f sdB = 1/(2π RON CS ) , where RON is 2.6. Discussions
Based on the foregoing analyses, Table 1 summarizes
the on-resistance of the switch. Based on its exponential
the influence of the most important parameters on
response, the time budget for the sampled voltage to settle
different error components. The change of the input signal
with an error less than 0.5 LSB for N-bit accuracy can be
VIN will cause either linear or nonlinear effects on
obtained from:
t
bandwidth, switch-induced error, and voltage droop,
−
1 which may result in distortions and degrade the ADC
e RON CS
< (4)
N +1
2 accuracy. A large value of sampling capacitance CS is
Also, assuming that a half-period of sampling clock is beneficial for signal integrity, but it is limited by the
used as the time budget, we express the allowable bandwidth requirement. On the other hand, a high supply
minimum f3dB as: voltage VDD is always favorable, but it increases the total
( N + 1) ln 2 power consumption. Finally, the decrease of the sampling
f 3 dB > fS (5)
π frequency fS provides large margin for jitter and bandwidth
where fS is the sampling frequency. design; it, however, may introduce a severe voltage droop.
Moreover, as the on-resistance of the switch is strongly
signal-dependent, it leads to varying tracking bandwidths. 3. ADC IMPLEMENTATION
Therefore, the minimum tracking bandwidth at certain The SA ADC is one of the most attractive architectures
input voltage needs to be ensured to satisfy Equation (5). for biomedical applications due to its simplicity and low
Otherwise the limited bandwidth may introduce nonlinear power consumption. The preceding analyses have been
errors to the sampling. used in the switch design for an ultra-low power 10-bit SA
ADC with a sampling rate of 1 kS/s in a standard 130 nm
2.5. Voltage Droop CMOS technology. To minimize the power, careful
Voltage droop originates as leakage from the sampling designs and optimizations of the entire ADC are
capacitor during the hold time. The switch leakage current necessary, while in this section we continue to focus on
is the major leakage contributor, of which the dominant the sampling switch design. The implemented ADC has
part is subthreshold leakage current with an expression 250
shown in [5].
Low
For an N-bit ADC, the total droop in the sampled
200
voltage has to be less than 0.5 LSB during the period of Vout
Leakage current [pA]
High
conversion. The maximum allowable signal change is:
VIN High
V FS 150
∆Vmax = (6)
2 N +1 VDC = VDD/2
Using half of the sampling clock period as the 100
conversion time, the maximum allowable leakage current
is given by: 50
V FS ⋅ C S ⋅ f S
I leak ≤ ( 7)
2N
0
Until now we have assumed that the leakage current is 0 0.1 0.2 0.3 0.4 0.5
constant during the conversion time. In most cases, Input voltage [V]
however, as the input voltage varies during the hold time, Figure 2. Simulated leakage current versus input voltage
the subthreshold leakage current will show strong ranging from 0 to VDD/2.

3. been sent for fabrication and further information about the 71 dB, which realizes more than 11-bit resolution.
ADC will be reported after the chip measurement. Besides the voltage droop, an insufficient tracking
bandwidth also introduces distortions. Thus, Equation (5)
3.1. SA ADC Architecture must be satisfied. Based on a simulation of the switch on-
The ADC, shown in Figure 3, consists of a comparator, resistance, we get the maximum RON value, at which the
a successive-approximation-register (SAR), and two minimum tracking bandwidth is found to be around 300
binary-weighted capacitive arrays. Differential kHz. Relating this value with a curve shown in Figure 6,
configuration is used to reject the common-mode error where the allowable minimum tracking bandwidth versus
components. During the first clock cycle, the differential sampling frequency is quantified based on Equation (5),
input voltages are sampled on the capacitor arrays. In the we observe that the proposed switch is more than
following nine clock cycles, the digital bits are decided sufficient for supporting a sampling frequency of 1 kHz.
one by one based on a binary-search algorithm. Figure 7 depicts the simulated average switch-induced
As the input voltages are directly sampled on the top- error voltage as a function of the input voltage. The
plate of the capacitor array, a stand-alone sampling average error voltage increases as the input voltage goes
capacitor is not needed. The array capacitors C0-C10 in high, which shows an almost linear variation. Moreover,
Figure 3 are realized as multiples of a 13.5-fF unit for the input level around 0.25V, the combination of
capacitor. The value is chosen to guarantee the 10-bit PMOS and NMOS cancels the total charge effect. The
linearity requirement. The total resulting array capacitance result is in concordance with Equation (3). Considering
is then approximately 14 pF, which is more than sufficient the maximum error voltage of 100 V, which is smaller
to limit the effect of the thermal noise according to than 0.5 LSB of the ADC, no particular charge injection
Equation (1). cancellation technique is employed. On the other hand,
using a differential architecture further suppresses the
3.2. Design and Characterization of CMOS Sampling common-mode disturbance and lowers the switch-induced
Switch
Although the low sampling rate relaxes the requirement
Magnitude [ dB ]
of jitter to be more than 10 ns according to Equation (2), it 0
Standard
still causes a large voltage droop. In order to reduce the -50 SNDR = 60 dB ENOB = 9.7 bit
subthreshold leakage current and keep the same on- -100
resistance, a CMOS switch, shown in Figure 4(b), is -150
designed with twice the size compared with the standard
0.1 0.2 0.3 0.4 0.5
switch, shown in Figure 4(a). In addition to increasing the Frequency [ f / f ]
s
transistor length, two-transistor stack [5] is also employed
Magnitude [ dB ]
to further reduce the leakage current. The signal-to-noise- 0
Proposed
and-distortion ratio (SNDR) of the switch output signal at -50 SNDR = 71 dB ENOB = 11.5 bit
1 kHz sampling frequency is simulated to evaluate the -100
leakage effect. Figure 5 demonstrates the simulated -150
SNDRs for both the standard and proposed switch. The 0.1 0.2 0.3 0.4 0.5
standard switch achieves SNDR of 60 dB, which is below Frequency [ f / f ]
s
10-bit resolution. The proposed switch achieves SNDR of
Figure 5. Simulated spectrums of the two switches at 1 V
supply voltage, 82 Hz input signal frequency, 1V input signal
swing and 1 kHz sampling speed.
7
10
Allowable minimum f3dB [ Hz ]
6
10
5
10
4
Figure 3. SA ADC architecture. 10
3
10
2
10 2 3 4 5 6
10 10 10 10 10
Sampling frequency [ Hz ]
Figure 6. Allowable minimum f3dB versus sampling frequency
(solid line). The horizontal dashed line represents the
minimum f3dB due to the switch on-resistance simulation for
Figure 4. CMOS sampling switch (a) Standard (b) Proposed. full-swing VIN at 1-V VDD.

4. Average switch-induced error voltage [ µV ]
100
80
60
SA ADC
40
20
0
-20
0 0.2 0.4 0.6 0.8 1
Input voltage [V]
Figure 7. Simulated average switch-induced error versus input Figure 8. Chip layout. Dimensions are 1 mm by 1 mm.
voltage.
error. 0
All the design constraints described in Section 2 are SNDR = 59 dB ENOB = 9.5 bit
-20
considered and related effects are characterized by
Magnitude [ dB ]
simulations. The proposed CMOS switch meets the -40
specification of the SA ADC. Moreover, the simple
architecture with only 4 transistors saves both silicon area -60
and power.
-80
3.3. Simulation of ADC Performance
-100
The layout of the SA ADC has been implemented,
shown in Figure 8. The core area is approximately 0.16 -120
mm2, which is dominated by the capacitor array. Post- 0.1 0.2 0.3
Frequency [ f / f ]
0.4 0.5
s
layout simulation was performed to characterize the
dynamic performance of the ADC. A typical low- Figure 9. Simulated spectrum at 1 V supply voltage, 55 Hz
input signal frequency, 1 V input signal swing and 1 kS/s
frequency discrete Fourier transform (DFT) output
sampling rate.
spectrum at 1-V supply is shown in Figure 9, for a full-
scale input at 55 Hz, sampling rate of 1 kHz, and 128 data Table 2. Summary of ADC performance
samples. The SNDR is 59 dB providing an ENOB of 9.5
bit. ADC performance
The total power dissipation of the SA ADC is 64 nW at Technology 130 nm CMOS
1-V supply and 1 kS/s output rate. Most of the power is Supply voltage 1V
consumed in the SAR logic (34 nW) and the capacitor Resolution 10 bit
array (28 nW), and the remaining 2 nW is consumed in the Input range Rail-to-rail
comparator. Sampling frequency 1 kHz
Table 2 summarizes the ADC performance. SNDR ( fIN = 55 Hz @ 1 kHz) 59 dB
ENOB ( fIN = 55 Hz @ 1 kHz) 9.5 bit
4. CONCLUSION Power dissipation 64 nW
General design constraints of CMOS sampling switch Die area (active) 0.16 mm2
are described and the analyses are used in the switch ADC power breakdown
SAR logic 34 nW
design for a low speed 10-bit SA ADC. With the proposed
Capacitor array 28 nW
switch and careful design of the entire ADC, the SA ADC Comparator 2 nW
consumes 64 nW at a sampling frequency of 1 kHz and
achieves 9.5 bit ENOB. The chip has been submitted for [4] C. J. B. Fayomi and G. W. Roberts, “Design and
fabrication and more detailed information about the ADC Characterization of Low-Voltage Analog Switch Without
will be reported after the final chip measurements. the Need for Clock Boosting,” in Proceedings of the
International Midwest Symposium on Circuits and Systems,
5. REFERENCES pp. 315–318, IEEE, 2004.
[1] L. S. Y. Wong, et al., “A Very Low-Power CMOS Mixed- [5] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand,
Signal IC for Implantable Pacemaker Applications,” IEEE “Leakage current mechanisms and leakage reduction
Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2446- techniques in deep-submicrometer CMOS circuit,” in Proc.
2456, Dec. 2004. IEEE, vol. 91, no. 2, pp.305 - 327, 2003.
[2] J. G. Webster, Medical Instrumentation Application and
Design, Wiley, 1998.
[3] F. Maloberti, Data Converters, Springer, 2007.