1. GATE STACK DESIGN BY: OreoluwaOdubela AdemakinwaAdetoro Axel Brugger

2. Contents Introduction and History of gate stack design Moore’s law and transistor development Gate oxide issues and High-k materials Poly-Si replacement and Gate stack processing issues Present gate stack design and future development Summary References and useful websites Questions/Comments.... Oreoluwa Odubela (200364760)

3. Introduction Basic CMOS Transistor The gate dielectric is at the heart of every MOS transistor device. MOS capacitors supply charge that switch the transistor on and off. To maintain/ improve the switching frequency as transistors shrink a smaller channel must carry the same amount of drive current IC manufacturers increase capacitance by making the dielectric thinner. Oreoluwa Odubela (200364760)

4. More Moore’s Law! Moore’s law [1] Transistor Development (1971-2015) Oreoluwa Odubela (200364760) *** Leakage current limited further scaling.

5. Intel’s microprocessors [2] Oreoluwa Odubela (200364760)

6. ELEC5200: Next Generation Silicon Technologies Gate Stack Design Gate Oxide Issues and High k Material Ademakinwa ADETORO/200500789

8. Intel is leading the race in this area with production of 32nm feature size in late 2009.

10. Junction depth

12. Gate Oxide issues and High K Material Reasons for Scaling: W=width of the channel , L=channel length µ=channel carrier mobility , Vg=gate voltage COX =capacitance density associated with gate dielectric when the underlying channel is in the inverted state Vd=drain voltage , Vt=threshold voltage

15. Increased gate –oxide leakage

16. Increased junction leakage

17. Lower output resistance

18. Lower transconductance

19. Interconnect capacitance

20. Higher sub threshold conduction

21. Process variation

23. Gate Oxide issues and High K Material Seeking new materials to drive Moore‘s Law Power -industry recognizes that high--k is needed!

25. Gate Oxide issues and High K Material High k Material and it advantage Benefit of using High k material compared with previous technology

27. Without a new dielectric material with increased thickness and a higher K value, Moore’s Law would inevitably hit a wall.

29. The power and heat issue is huge and industry has been searching for solutions for a long time. Intel has solved a major part of the problem by integrating new materials into transistors.

30. Intel has achieved world record performance at dramatically reduced leakage with its new transistor .

33. Reduction of overlap capacitances (Miller effect)

34. Reduction of threshold voltage by 1.1V (~30%) due to a lower work function Φ

35. 3-5x faster and 3-5x less power consumption

36. Cost effective: SGT uses ~ ½ the silicon area

38. Thermal stability requirements to be 1000 °C for 10s (ITRS)

39. Gate leakage and yield determine performance

40. Area dependence suggests yield failures for higher gate-leakage

42. Result: Depletion at the dielectric interface when transistor channel is in inversion

43. What to do about it ?

44. higher inversion capacitance required

46. Reduction of electron mobility in metal gate / high-k gate dielectric stacks compared to Poly-Si/SiO2 gate stacks.

48. Mobility increases with annealing temperature

50. Future Development According to Moore’ law we should see a trend in transistor development as such: High-k metal gate structures will be more prevalent than Si02 There may be a move from planar CMOS to the use of tri-gate (Intel) and FinFET (AMD, IBM, Motorola) transistors Oreoluwa Odubela (200364760)

53. Intel’s High-k/Metal Gate Announcement November 4th, 2003 Presentation Paper.

54. Seminar on High K Dielectric Solution for MOSFET scaling Final Report by GECKozhikkode

55. Challenges in gate stack engineering by Robert W. Murto, Mark I. Gardner, George A. Brown, Peter M. Zeitzoff, Howard R. Huff, International Sematech, Austin, Texas

57. ‘High k-dielectrics’, Michel Houssa

59. Questions/ Comments OreoluwaOdubela (200364760) Thank You!!!