Vguruquickoverview_win_dec13

VGuru™ Quick Over View

SkandVLSI, 101 Meenakashi Enclave, 13 F Main, HAL 2 Stage, Bangalore – 560 008
Phone: +91-90191-91204; +91-93421-07608; Email: vguru@skandvlsi.com; Web: www.skandvlsi.com;

1. Works on MS Windows 4

2. Live Guidance like a Guru...................................................................................................................... 4

3. Visual Prompts and Status .................................................................................................................... 6

3.1 Number Panel ..................................................................................................................................... 6

3.2 VErify Panel ......................................................................................................................................... 7

4. VGyan™ Window: Detailed Knowledge on Verilog | VHDL .................................................................. 8

Features of VGyan Window: ..................................................................................................................... 8

4.1 Links.................................................................................................................................................... 8

4.2 Search Topic .................................................................................................................................. 8

4.3 Tips ...................................................................................................................................................... 9

4.4 Closing and Re-opening VGyan Window: ......................................................................................... 10

5. Learn Verilog|VHDL along with Digital logic and CMOS logic gates ................................................... 11

6. Design and Testbench Wizard............................................................................................................. 13

7. Practice what you have Learnt and Self Assess .................................................................................. 14

8. Teach ................................................................................................................................................... 14

9. ASIC Flow : LearnPracticeTeach.................................................................................................. 14

10. Design Samples ............................................................................................................................... 15

11. Verilog Code - Examples ................................................................................................................. 15

11.1 Good Code ...................................................................................................................................... 16

11.2 Syntax Error..................................................................................................................................... 16

11.3 non-Recommended ........................................................................................................................ 16

12. Simulating the Design coded .......................................................................................................... 16

13. How to Target to FPGA : VGuru Guidance ...................................................................................... 20

Contact for help: vguruhelp@skandvlsi.com VGuru is licensed as node locked for Verilog and/or VHDL

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Welcome to VGuru™ Verilog | VHDL Learn  Practice  Teach
You are now, the proud “Shishya”1 of VGuru™ 2.

VGuru™ , first of its kind in the world, in the field of VLSI education, that guides, helps and
makes proficient , like a GURU, who help succeed.

Today, a graduate should acquire fluent knowledge in Verilog and VHDL languages to enter
and excel in the VLSI industry. Industry’s expectation is quality man-power from academia. To
be INDUSTRY READY, a graduate should be learning Verilog/VHDL with industry best practices,
along with other related subject viz., CMOS Digital logic and prepare self for the academic
exams.

Product Look n Feel:
1.1 3 3 3 2.2 2.1
Tabs Syntax Errors Best Practices Non-recommended Search topic Links
Practices
Application window
5
Menu

HDL mode
3

VNext pop-up

1.2
Number panel

Design File Browser Main Editor Window VGyan Window
4 1 2


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1. Works on MS Windows
Learning Verilog, VHDL for the students, faculty and new entrants to the VLSI industry, involves
juggling around different operating systems, different windows, iterative editing etc. VGuru™,
works on MS windows.
a. Removes the necessity to move to different operating system.
b. Removes the necessity to open multiple windows to edit the Verilog/VHDL code and
windows for compilation
c. Removes necessity to switch setup and multiple windows to learn Verilog and VHDL
 To learn both Verilog and VHDL languages, simultaneously, no Hassle of changing
lot of setup. Just Click 

Active Tab Inactive Tab Inactive Tab Inactive Tab for
for Verilog for VHDL for CMOS Truth Table

The active Tab mode (Verilog/VHDL/CMOS/Truth Table) is shown on the VErify panel

2. Live Guidance like a Guru
As soon as you start your coding in Verilog or VHDL, VGuru™ gives live guidance in the form of
“VGuru Next”
a. Syntax Guidance : You don’t need to remember any syntax or refer to books


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Window showing, what to write next after module keyword. Also shows LRM syntax of module. There is a
non-recommended practice shown by “thumbs down” icon, i.e. Design started without comments

b. Semantic Errors : Semantic errors are not syntax related but logic related. Eg. Latch
inference, unused signals etc.
c. Recommended Practice Guidance : Help you to be INDUSTRY READY, shown as
d. Non-recommended Practice Guidance : Help you to be INDUSTRY READY, as
e. Syntax Guidance: No need to separately compile and correct errors separately. As soon
as you make a syntax error, VGuru™ immediately underlines. Shown as
 You will never continue the design with Syntax/Semantic errors. You correct as
soon as VGuru™ prompts. Saves lots of iterations

f. Semantic Error Guidance: Though Syntactically correct, semantics of Verilog or VHDL is
important for correct design


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Window showing, semantic guidance for empty process. Also shows What to write next. There is a
recommended practice shown by “thumbs up” icon, i.e. keywords in lower case

3. Visual Prompts and Status

3.1 Number Panel
While you Learn, Practice or Teach Verilog or VHDL, the number panel Visually shows the
following
Recommended Practices
Non Recommended Practices
Syntax Errors in the current line


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You can place the mouse on these symbols to know the syntax error.
Line No.

Place Cursor on syntax error
Syntax Error (underlined red) to know the
exact error. Entity names are
different here!

 Visually represents the lines where syntax errors are present along with
Recommended Practices and Non-Recommended Practices.

3.2 VErify Panel
VErify Panel gives instant Visual Report On

Next Syntax Error
Previous Syntax Error
Number of Syntax Errors in the active Tab
Number of Recommended Practices You followed (refer to 2.3)
Number of Non-Recommended Practices You followed (refer to 2.3)
Current Active Tab Mode is Verilog
Current active Tab Mode is VHDL
CMOS practice window: Logic Gates and Stick Diagrams
Truth Table Practice: Logic Gates and input/output Waveforms

 VGuru™ on-fly VErify the code, you enter and give instant feedback about Syntax
Errors. VGuru™ is the first product in the world, which can VErify quality of your
code and guides you.


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4. VGyan™ Window: Detailed Knowledge on Verilog | VHDL
VGyan window, at the right side of coding window, gives more details on each current word you
typed or the mouse action. This window as appropriately called VGyan (Wisdom) window,
contains all learning. Scroll down to read completely.

Features of VGyan Window:

4.1 Links
Keys words in the VGyan explanation has html links you can click on to learn more about the
topic. This helps in getting information without moving out of the application. For example, to
learn about black box, click on the link and you will see as below

Click to open default
browser automatically
searching for keyword.

 You learn as you go

4.2 Search Topic
VGyan provides pull down menu search, to quickly access information about various topics it
teaches. Choose from drop down what you want to learn without actually typing that word in
the design code. For example if you want to learn about always keyword in verilog, without
actually type a valid always block, just pull down and select always keyword related topics and
learn.


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 Helps to quickly brush up all the topics for exams or interviews.

4.3 Tips
Tips are very useful information for you to be Industry Ready. VGuru™ team worked with
industry, to gather information on these. These tips are unique and mostly do not find in
any textbooks. VGuru™ is here with the large collection of tips to teach.
Tips are categorized as:

Recommended Practices
Non Recommended Practices

Points to remember.
Points where caution is needed.

Industry Related tip, may not be widely used, but good to know.

Synthesis and Simulation related Tips

Book icon, Represents info about Syntax. You don’t need to refer to Text Books


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VGyan window when you type always keyword in verilog tab

 You gain Industry exposure, along with, learning for your Exam Courses.

4.4 Closing and Re-opening VGyan Window:

You can close the VGyan Window to make more room for your coding and make it appear,
when ever needed to learn more about Verilog | VHDL you are coding. You can use the
following methods:

a. Click on the VGyan Window top right corner to close.
b. Use “Show” menu dropdown to un-check VGyan box. 
c. To make it re-appear check the VGyan box. 
You will get back to the latest VGyan for what you are typing.

 Close the VGyan and start memorizing the info VGyan would have given for a
Verilog or VHDL code. Helps as a “Self Test”


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5. Learn Verilog|VHDL along with Digital logic and CMOS logic
gates
Verilog or VHDL is means of coding a digital circuit and its very important to connect it to the
truth table of fundamental gates, AND, NAND, OR, NOR, XOR, NOT…etc.

VGuru™ provides the frame work to practice the truth tables and CMOS equivalents of these
gates. You can check your understanding of the input and output logic values from Truth Table
practice and learn how to draw a digital wave form.

NAND truth table practice

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CMOS logic Gates Practice helps to understand underlying Logic Gates circuitry. CMOS practice,
helps understand MOS transistor connections and their ON/OFF state for a set of logic inputs.
VGuru™ teaches how to draw a Stick Diagram for a Logic Gate Transistor Layout. Layout
determines how effectively a chip can pack more transistors. More Transistors, More
functionality…Stick Diagram forms the basis for learning how bigger Electronic Chips layout is
done.

NAND CMOS practice and Learning Stick Diagram

 Practice Sessions are linked to Verilog or VHDL coding. As soon as you instantiate
gate primitives, Truth Table window is opened.


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6. Design and Testbench Wizard
Quickly create design or testbench or both by filling interactive popup. In VGuru™ advanced you
can just right click on the main coding window to create testbench for the design you are coding.

 Lot of coding is reduced. The testbench template created with all the required
guidance in comments. Just enter the test vectors, its up for simulation

Right Click in the window and
Choose Create TestBench. A
testbench template with the
design is created

 Lot of coding reduced

Test bench also can be created by clicking on “Run Simulation” for a design, in the popup
window as shown above.


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7. Practice what you have Learnt and Self Assess
VGuru™ allows you to practice what you learnt from VGuru™. You can turn off Live Guidance on
Syntax Errors, Semantic Errors, Recommended and Non-Recommended Practices.

The Coding window becomes just plain editor, VErify panel does not show any , , . Once
you are done with coding switch on all to know the Quality of the code.

 Refine the knowledge as you go

8. Teach
VGuru™ is the first software product that teaches you how to be proficient with Verilog or VHDL
language. VGuru™ can also be used for teaching.

9. ASIC Flow : LearnPracticeTeach
VGuru™ has an integrated ASIC flow learn-practice-teach module. Students can quickly learn
flow steps and important activity in each step of the ASIC flow.


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The module is interactive. Starts with Spec step, and as you understand each step in detail from
the VGyan window, click on the current step to go to the next step. At any stage, place a cursor
on any step to know key words in that step by way of a popup, and details in the right window.

 Easy learning of key concepts in each step. Easy review for exams.

10. Design Samples
VGuru™ has couple of examples for the beginners to start thinking of Verilog coding for a
particular functionality. Click on Examples menu item to follow the instructions, prompted at
the VGyan Window (right side of the main coding window).

11. Verilog Code - Examples
A set of Verilog examples provided in the VGuru™ working directory, help to be familiar with the
Software and how easy it is to do projects with VGuru™


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11.1 Good Code
Examples provided in the good code directory, does not have any syntax errors. Learners are
encouraged to practice these examples by using VGuru™.

11.2 Syntax Error
Examples in this directory, have syntax error. Double click open each verilog file and see syntax
errors visually, by looking at . Place cursor on the Red underlined places to learn about syntax
errors, see how fast you correct them. The same would have taken lot of iterations of edit
compile, and switching windows and operating system at times.

11.3 non-Recommended
Examples in this directory, have non recommended practices. Double click open each verilog file
to find non-recommended practices used in the code, by looking at . Place Cursor on the icon,
against each line and find whats the non-recommended practice. Remove all non-recommended
practices and make the code with recommended practices.

 VGuru™ is the only software in the world, for Verilog | VHDL, to guide with
recommended and n0n-recommended Industry practices, while learning.

12. Simulating the Design coded
VGuru is integrated with the free GPL simulators for both Verilog and VHDL. The simulation
guidance is integrated in to VGuru.

Once design is coded, right click on the window to open a popup, Click on Run Simulation. A
Window with the following options will appear.

Select a Test Bench on Create a Test Bench.

Once testbench is created, edit the testbech by looking at the extensive comments provided in
the template by VGuru. Once finished entering vectors for the inputs, at the places indicated by


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comments, right click on the window to open popup menu, Click on Run Simulation. The
following will appear

Make sure the first three are green. Other wise go back to testbench and uncomment as
appropriate. Click OK, if all the first three are green.

The following popup appear automatically selecting the design and testbench. To automatically
select the Design for a testbench same name as entity or module to be used for the file
names.

If you don’t see the design and testbench shown automatically selected, add it manually by
clicking appropriate button.

Select the black or white back ground.

Click on “Run For”, to see


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You can view the log. If the simulation is successful, in the log you see .VCD file getting dumped.
The generic name will be testbench_name.vcd.

Once you close the logfile window, need to select the vcd to show the waveform.

Select the appropriate VCD file and you see as below


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Select the design on left top to see all the signals below the window. Drang and drop each signal
into display window. Click on zoom to fit icon to see all signals at one time.

Close the waveform window, and enter more vectors to repeat the simulation.

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 Writing the Verilog|VHDL code and seeing the results now takes significantly less
time.

13. How to Target to FPGA : VGuru Guidance
VGuru provides FPGA implementation guidance as well. This helps concentrate on the results of
the design rather than understanding the Board and other software.

 Need the following software

o Xilinx ISE

o Adept USB Download

o Nexys2 Board

Setup for FPGA targeting. Click on FPGA menu and setup to select appropriate resources.

Press OK.

Open the design file or code the design in the editor window. Right click inside window to open
pop up and select FPGA Implementation


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Observe the following pop up, select the Development board. VGuru currently integrates only
Spartan-3E 500K board.

All the required values are filled automatically.

 VGuru saves lot of hard work in creating the setup file with different values.


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Once clicked OK, project will be compiled with the following popup if successful.

Press OK, to map the inputs and outputs to the LEDs and Switches on the Spartan-3E board.

 . VGuru simplifies this to make it visually easy. Mannually creating a UCF file is
cumborsome

 Right click on each swith and LED to assign the inputs ad outputs respectively.


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Assign all the inputs and outputs and click OK, the popup should look like the following fig.

Click Yes. The implementation window opens. Click on Start.


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There can be failure because of TEMP declaration, this is usual and Click on Start once more.
You will see

Click on OK, to open Adept Software Automatically,


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Follow the instructions to download to the board.

 Very easy to take you simple Verilog or VHDL code, to the FPGA board, FOCUSSIN ONLY
ON VERILOG CODING, nothing else.


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Vguruquickoverview_win_dec13

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