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Introduction to VHDL M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi
Domains of Description : Gajski’s Y-Chart Behavioral domain Structural domain Physical domain Level of  abstraction VHDL models
VHDL Development ,[object Object],[object Object],[object Object],[object Object]
HDL Requirements ,[object Object],[object Object],[object Object],[object Object]
Abstraction ,[object Object],[object Object],[object Object],[object Object]
Modularity ,[object Object],[object Object],[object Object],[object Object]
VHDL Example a b c AND
VHDL Description: AND gate ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrency in  VHDL Descriptions signals process 1 process 2 process n signals
Concurrent and Sequential Computations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Hierarchy in VHDL
Modeling Styles in VHDL   M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
Modeling Styles ,[object Object],[object Object],[object Object],[object Object],[object Object]
Modeling Choices in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Structural Description ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Behavioral Description ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Statements in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 1-bit Full Adder ,[object Object],[object Object],[object Object],[object Object],X Y Cin Sum Cout FullAdder
Example: 1-bit Full Adder (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Adder ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Adder (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Comparator ,[object Object],[object Object],[object Object],[object Object],[object Object]
Structural Description (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 1-bit Comparator  (data flow) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
References ,[object Object],[object Object],[object Object],[object Object],[object Object]
Behavioral Description in VHDL   M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
Modeling Styles ,[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Statements in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: D Flip-Flop ,[object Object],[object Object],[object Object],[object Object],D CLK Q QN DFF
Example: DFF (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Conditional Assignment: 4 to 1 Multiplexer ,[object Object],[object Object],[object Object],[object Object],x0 x1 x2 x3 sel y
CASE Statement:  4 to 1 Multiplexer Case sel is   when  0 =>  y <= x0 when  1 =>  y <= x1 when  2 =>  y <= x2 when  3 =>  y <= x3 end case   x0 x1 x2 x3 y
Variables And Signals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Variables And Signals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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VHDL

  • 1. Introduction to VHDL M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi
  • 2. Domains of Description : Gajski’s Y-Chart Behavioral domain Structural domain Physical domain Level of abstraction VHDL models
  • 3.
  • 4.
  • 5.
  • 6.
  • 7. VHDL Example a b c AND
  • 8.
  • 9. Concurrency in VHDL Descriptions signals process 1 process 2 process n signals
  • 10.
  • 12. Modeling Styles in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26. Behavioral Description in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
  • 27.
  • 28.
  • 29.
  • 30.
  • 31.
  • 32. CASE Statement: 4 to 1 Multiplexer Case sel is when 0 => y <= x0 when 1 => y <= x1 when 2 => y <= x2 when 3 => y <= x3 end case x0 x1 x2 x3 y
  • 33.
  • 34.