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Day2.Combinational Logic

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Ron Liu
Ron Liu

This document discusses various digital logic components including combinational logic gates, decoders, multiplexers, priority encoders, comparators, adders, and arithmetic logic units. It provides examples of Verilog code for 7-segment displays, decoders, and ALUs. It also outlines several logic design labs involving testing components like counters, decoders, multiplexers, and ALUs using stimulus and response monitoring.

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Logic & Combinational Logic
LAB: Logic Operation test_counter dut counter Stimulus and control count[7:0] clk reset enable counter Response logic_block logic_out monitor A verification B logic_block C C B A logic_out 0 0 0 1 assign 0 0 1 1 !: NOT 0 1 0 1 0 1 1 1 &&: AND 1 0 0 0 ||: OR 1 0 1 0 1 1 0 0 1 1 1 1
Decoder I1 I0 Y0 Y1 Y2 Y3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
7 segment decoder Binary a b c d e f g dp 0000 0 0 0 0 0 0 1 1 0001 1 0 0 1 1 1 1 1 ......
MAX II 7 segment 實驗板 當Common pin 為高準位時，表示啟動其中 ● 一組七段顯示器 當Segment pin 為低準位時，表示點亮那一 ● 段LED
Verilog Code case (in) 4'h0: seg_out = 8'b1100_0000; // 0 active low '0' 4'h1: seg_out = 8'b1111_1001; // 1 4'h2: seg_out = 8'b1010_0100; // 2 4'h3: 4'h4: ............................... 4'hf: default: end case;
LAB: Decoder test_counter dut counter Stimulus and control count[7:0] clk reset enable counter Response use led_dec monitor seg0 procedure verification timing control led_dec a = seg(0); seg1 b = seg(1); c = seg(2); d = seg(3); e = seg(4); f = seg(5); g = seg(6); dp = seg(7)
Encoder I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 IDLE 00000000 x x x 1 10000000 0 0 0 0 01000000 0 0 1 0 IDLE = (!I0) * (!I1)....(!I7) = !(I0+I1+...I7) 00100000 0 1 0 0 00010000 0 1 1 0 Y0 = I1 + I3 + I5 + I7 00001000 1 0 0 0 Y1 = I2 + I3 + I6 + I7 00000100 1 0 1 0 Y2 = I4 + I5 + I6 + I7 ................
Priotity Encoder I7 = R7 I6 = R6 * (!R7) I5 = R5 * (!R6) * (!R7) ...... I0 = R0 * (!R1).....(!R7) Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7
Multiplexer, De-Mux
Comparator AGTBOUT = (A>B) + (A=B) * AGTBIN AEQBOUT = (A=B) * AEQBIN ALTBOUT = (A<B) +(A=B) * ALTBIN
LAB: Mux test_counter dut counter Stimulus and control count[7:0] clk reset enable counter seg0 Response use led_dec seg1 monitor procedure verification timing control sel_data seg0 1 seg1 led_seg[7:0] 0 sel_data
LAB: Encoder, Priority Encoder, Comparator test_counter dut cntgt64 counter Stimulus and control count[7:0] clk reset enable counter seg0 use led_dec seg1 Response procedure monitor timing control verification seg0 1 led_seg[7:0] seg1 0 event[7:0] IDLE Event encoder Y[2:0]
Parity Check
Adder Half Adder ● S=X^Y COUT = X*Y Full Adder ● S = X ^ Y ^ CIN CO = X*Y + X*CIN + Y*CIN
Subtractor A3 B3 A2 B2 A1 B1 A0 B0 1
ALU aluo[4:0] A[3:0] B[3:0] ALU S[1:0] S[1:0] A[3:0] B[3:0] aluo[4] aluo[3:0] 進位 00 A B A+B 借位 01 A B A-B 10 A B 0 A AND B 11 A B 0 A OR B
LAB: new project, ALU lab2 dut Stimulus and control aluo[4:0] S[1:0] A[3:0] ALU B[3:0] Response monitor verification
Appendix ALU module alu ( A, B, sel, aluo); input [3:0] A, B; input [1:0] sel; output [4:0] aluo; reg [4:0] aluo; always @(A or B or sel) begin if (sel == 0) // how about case aluo = A+B; else if (sel == 1) aluo = A-B; else if (sel == 2) aluo = A & B; else aluo = A | B; end endmodule

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Day2.Combinational Logic

  • 2. LAB: Logic Operation test_counter dut counter Stimulus and control count[7:0] clk reset enable counter Response logic_block logic_out monitor A verification B logic_block C C B A logic_out 0 0 0 1 assign 0 0 1 1 !: NOT 0 1 0 1 0 1 1 1 &&: AND 1 0 0 0 ||: OR 1 0 1 0 1 1 0 0 1 1 1 1
  • 3. Decoder I1 I0 Y0 Y1 Y2 Y3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
  • 4. 7 segment decoder Binary a b c d e f g dp 0000 0 0 0 0 0 0 1 1 0001 1 0 0 1 1 1 1 1 ......
  • 5. MAX II 7 segment 實驗板 當Common pin 為高準位時，表示啟動其中 ● 一組七段顯示器 當Segment pin 為低準位時，表示點亮那一 ● 段LED
  • 6. Verilog Code case (in) 4'h0: seg_out = 8'b1100_0000; // 0 active low '0' 4'h1: seg_out = 8'b1111_1001; // 1 4'h2: seg_out = 8'b1010_0100; // 2 4'h3: 4'h4: ............................... 4'hf: default: end case;
  • 7. LAB: Decoder test_counter dut counter Stimulus and control count[7:0] clk reset enable counter Response use led_dec monitor seg0 procedure verification timing control led_dec a = seg(0); seg1 b = seg(1); c = seg(2); d = seg(3); e = seg(4); f = seg(5); g = seg(6); dp = seg(7)
  • 8. Encoder I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 IDLE 00000000 x x x 1 10000000 0 0 0 0 01000000 0 0 1 0 IDLE = (!I0) * (!I1)....(!I7) = !(I0+I1+...I7) 00100000 0 1 0 0 00010000 0 1 1 0 Y0 = I1 + I3 + I5 + I7 00001000 1 0 0 0 Y1 = I2 + I3 + I6 + I7 00000100 1 0 1 0 Y2 = I4 + I5 + I6 + I7 ................
  • 9. Priotity Encoder I7 = R7 I6 = R6 * (!R7) I5 = R5 * (!R6) * (!R7) ...... I0 = R0 * (!R1).....(!R7) Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7
  • 11. Comparator AGTBOUT = (A>B) + (A=B) * AGTBIN AEQBOUT = (A=B) * AEQBIN ALTBOUT = (A<B) +(A=B) * ALTBIN
  • 12. LAB: Mux test_counter dut counter Stimulus and control count[7:0] clk reset enable counter seg0 Response use led_dec seg1 monitor procedure verification timing control sel_data seg0 1 seg1 led_seg[7:0] 0 sel_data
  • 13. LAB: Encoder, Priority Encoder, Comparator test_counter dut cntgt64 counter Stimulus and control count[7:0] clk reset enable counter seg0 use led_dec seg1 Response procedure monitor timing control verification seg0 1 led_seg[7:0] seg1 0 event[7:0] IDLE Event encoder Y[2:0]
  • 15. Adder Half Adder ● S=X^Y COUT = X*Y Full Adder ● S = X ^ Y ^ CIN CO = X*Y + X*CIN + Y*CIN
  • 16. Subtractor A3 B3 A2 B2 A1 B1 A0 B0 1
  • 17. ALU aluo[4:0] A[3:0] B[3:0] ALU S[1:0] S[1:0] A[3:0] B[3:0] aluo[4] aluo[3:0] 進位 00 A B A+B 借位 01 A B A-B 10 A B 0 A AND B 11 A B 0 A OR B
  • 18. LAB: new project, ALU lab2 dut Stimulus and control aluo[4:0] S[1:0] A[3:0] ALU B[3:0] Response monitor verification
  • 19. Appendix ALU module alu ( A, B, sel, aluo); input [3:0] A, B; input [1:0] sel; output [4:0] aluo; reg [4:0] aluo; always @(A or B or sel) begin if (sel == 0) // how about case aluo = A+B; else if (sel == 1) aluo = A-B; else if (sel == 2) aluo = A & B; else aluo = A | B; end endmodule