1. 1.
a. Name the interrupt that has the highest priority and its call location.
Answer: TRAP, XX24H
b. EI
MVI A, 00011010B
SIM
From the instruction above, can you determine which interrupt/interrupts is/are enabled?
Answer: RST 5.5 only. RST 7.5 are not enabled due to bit D4=1. If bit D4=1, RST 7.5 flip-flop is reset OFF.
c. Name all of the software interrupts in 8085.
Answer: RST 0,RST 1,RST 2,RST 3,RST 4,RST 5,RST 6,RST 7
d. What is the RST for TRAP?
Answer: RST 4.5 is known as TRAP
2.
a. Explain the difference between a nonmaskable and maskable interrupt
Ans:
maskable: the microprocessor can ignore or delay a maskable interrupt request if it is
performing some critical task.
Nonmaskable: the microprocessor has to respond to a nonmaskable request immediately.
b. List the 8085 vectored interrupts, nonmaskable interrupt and their vectored memory locations.
Ans: RST7.5 maskable 003C
RST6.5 maskable 0034
RST5.5 maskable 002C
TRAP nonmaskable 0024
c. List the interrupt(s) that is/are:
i. level sensitive only Ans: RST5.5, RST6.5
ii. edge sensitive only RST7.5
iii. both level and edge sensitive TRAP
d. How long can the INTR pulse stay high?
Ans:
The INTR pulse can remain high until the interrupt flip-flop is set by the EI instruction in the service routine. If
it remains high after the execution of the EI instruction, the processor will be interrupted again, as if it were a
new interrupt.
1. Which interrupt is not level sensitive in 8085?
RST7.5 is a raising edge-triggering interrupt
2. a) Calculate the time delay for the program given below, when clock period = o.5us
MVI C, F0H
LOOP: DCR C
JNZ LOOP
MVI C, EF ---------------7T (no of state)
LOOP: DCRC -------------- 4T(no of state)
JNZ LOOP -------------- 10/7 T(no of state)

2. Time delay TD = (14 X 0.5X10^-6 X 240)-3 X 0.5us + 7 X 0.5us
= 1.68ms
b) Write a time delay program using 16-bit register.
LXI H, 2345H
LOOP: DCX H
MOV A, C
ORA B
JNZ LOOP
-------------------------------------------------ggjaya^^---------------------------------------------
-----------------------
1.a)
Question:
Calculate the total T-states.
MVI C, 0 7T
LOOP: DCR C 4T JNZ LOOP 10/7T
Answer:
Total T-state = 7 + 255(4+10) +(4+7) = 3588
2(a) List the four instructions which control the interrupt structure of the 8085 microprocessor.
Ans:-
 DI ( Disable Interrupts )
 EI ( Enable Interrupts )
 RIM ( Read Interrupt Masks )
 SIM ( Set Interrupt Masks )
2(b) Explain priority interrupts of 8085.
Ans:-The 8085 microprocessor has five interrupt inputs. They are TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. These
interrupts have a fixed priority of interrupt service. If two or more interrupts go high at the same time, the 8085 will
service them on priority basis. The TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5. The priority of
interrupts in 8085 is shown in the table.
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5
----------------------------------------WKN,NJW,PYT,PCY & OSL---------------------------------------
1 a)List out all interrupt inputs for 8085 microprocessor.
INTR , RST5.5 , RST 6.5 , RST7.5 , TRAP
1b) Write down the name of the non-vectored interrupt and non-maskable interrupt.
non-vectored interrupt -------- INTR
non-maskable interrupt --------- TRAP
2a) Write out the design process of counter.

3. - Loading appropriate number in register
- Use INR and DCR instruction
- Established loop to update account
- Check the final count number
-------------------------------------------------LCY,LCH,HMY,NYC,RAY--------------------------------------------------
1. a) Can the microprocessor be interrupt again after the completion of ISR?
Yes.
b) Why?
Because it is up to us to enable / allow the interrupt or not.
2. How long must INTR remain high?
The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must
remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional
CALL instruction which requires 18 T-states.
-----------------------------------------------------GGLem---------------------------------------------------------
1. A "MVI" instruction is used, how long time does it take to run in 2MHz?
[ hint : MVI use 7 T-states ]
Ans : time delay to complete = No. of T states/ Frequency
time taken = 7 / 2 MHz = 3.5us
2. when implementing INTR interrupts, it needs to remain active for a certain time. Given that the 8085 microprocessor
operates at frequency of 3.5MHz, how long must the INTR remains active? [ Hint : the longest instruction for 8085 is 18
T states ]
Ans : since the microprocessor check INTR line, one clock cycle before the last T state of each instruction, and from the
hint, the longest instruction for 8085 is 18 T states. This means that INTR lines need to hold at least 17.5 T states as
INTR line needs to remains active long enough for the longest instruction. The time for INTR line to remain active is :
T(INTR) = 1 / F * 17.5 = 1 / 3.5 M * 17.5 = 5 us
---------------------------------------- Ola.Hajar.Fiti.Chelvan.Davin--------------------------------------
QUESTION 1: How do we allow multiple devices to interrupt using the INTR line?
ANSWER:
1. The microprocessor can only respond to one signal on INTR at a time.
2. Therefore, we must allow the signal from only one of the devices to reach the microprocessor.
3. We must assign some priority to the different devices and allow their signals to reach the microprocessor according
to the priority.
QUESTION 2 : Write a program that reads in data from input ports 85H and 86H, saves them on the
stack, transfer control to a subroutine (SUBR1), and upon return from the subroutine, pops the data from
the stack and stores the data at memory locations 2006H and 2007H.
ANSWER/SOLUTION:
IN 85H
MOV B, A
IN 86H
MOV C, A

4. PUSH B
CALL SUBR1
POP B
MOV A, B
STA 2006H
MOV A, C
STA 2007H
HLT
----------------------------------------cz chalson fun chok chris royce--------------------------------------
1. Which interrupt in the 8085 microprocessor has memory?
ANS ~ THE RST 7.5 IS THE ONLY INTERRUPT THAT HAS MEMORY. IF A SIGNAL ON THE RST 7.5 ARRIVES WHILE IT
IS MASKED , A FLIP FLOP WILL REMEMBER THE SIGNAL. WHEN IT IS UNMASKED, THE MICROPROCESSOR WILL BE
INTERRUPTED EVEN IF THE DEVICE HAS REMOVED THE INTERRUPT SIGNAL.THE FF WILL AUTOMATICALY RESET
WHEN MICROPROCESSOR RESPONDS TO AS RST 7.5 INTERRUPT.
2. i try post it as picture bcuz the question2 is abt filing the blanks in table form
_________________________ijatmata,ijatromeo,fahmi,kuduih,syahmi_______________________
The 8085 microprocessor has two pin to handle serial communication called SOD (serial output Data) and SID(Serial
input data) . What is the instruction to use for data transfer?
ANS: SIM and RIM
SIM is used to transfer data out of 8085 serially
RIM is used to read serial data on the SID pin
What is an interrupt?
ANS: An interrupt is an external or internal event that interrupt the microcontroller to inform it that devices need it
service
----------------------------------------------------------------------------------------------------------------------------- -----
Question
1. Design an 8-bit combined counter. The counter acts as a Johnson counter when input is HIGH and ring counter when
input is LOW
2. What are the hardware interrupts in 8085? What are the priorities and the triggering method for each interrupt?
Solution
1. START: IN PORT A
ANI 01H
JZ JOHNSON
JMP RING
JOHNSON: MVI B, 00H
OUT PORT B
CALL DELAY
JOHNSON_1: MOV A,B
STC
RAL
MOV B,A
OUT PORTB
CALL DELAY
CPI FFH
JNZ JOHNSON_1
JOHNSON_0: MOV A,B

5. STC
CMC
RAL
MOV B,A
OUT PORT B
CALL DELAY
CPI 0
JNZ JOHNSON_0
JMP START
DELAY: MVI D, FFH
LOOP: MVI E,FFH
LOOP1: DCR E
JNZ LOOP 1
DCR D
JNZ LOOP
RET
RING: MOV B, 01H
OUT PORT B
CALL DELAY
RING1: MOV A,B
RLC
MOV B,A
OUT PORT B
CALL DELAY
CPI 80H
JNZ RING1
JMP START
2.
INTERRUPT NAME PRIORITY TRIGGERING METHOD
TRAP 1 LEVEL AND EDGE SENSITIVE
RST 7.5 2 EDGE SENSITVE
RST 6.5 3 LEVEL SENSITVE
RST 5.5 4 LEVEL SENSITIVE
INTR 5 LEVEL SENSITIVE
--------------------------------------------------------------------------------------------------------------------------------
Questions:
1. Fill in the blanks with ‘Yes’ or ‘No’.
Interrupt name
Maskable
Vectored
RST 5.5
Yes
Yes
RST 6.5
Yes
Yes
RST 7.5
Yes
Yes
TRAP
No

6. Yes
INTR
Yes
No
2. Rearrange the process of the 8085 non-vectored interrupt.
The 8085 checks for an interrupt during the execution of every instruction
2
Upon receiving the INTA signal, microprocessor saves the memory location of the next instruction on the stack and the
program is transferred to ‘call’ location (ISR call) specified by the RST instruction.
5
The interrupt process should be enabled using the EI instruction.
1
INTA allows the I/O device to send a RST instruction through data bus.
4
ISR must include the ‘EI’ instruction to enable the further interrupt within the program.
7
RET instruction at the end of the ISR allows the microprocessor to retrieve the return address from the stack and the
program is transferred back to where the program was interrupt.
8
Microprocessor performs the ISR
6
If INTR is high, microprocessor completes current instruction, disable the interrupt and sends INTA (interrupt
acknowledgement) signal to the device that interrupted.
3
-----------------------------------farhan,redza,fernandez,iqbal,alif-------------------------------------------
1. Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.
1.1 Classify the interrupt types found in microprocessor 8085 and give examples.
1.2 What is the difference between vectored and non-vectored interrupts?
1.3 List the priority of interrupts of 8085.
2. Define instruction cycle, machine cycle and T-state
Answers
1.1 Interrupts can be classified into 2 categories which are maskable
interrupts and non –maskable interrupts.
Examples are:
(a) INTR (maskable)
(b) RST 5.5 (maskable)
(c) RST 6.5 (maskable)
(d) RST 7.5 (maskable)
(e) TRAP (non-maskable)
1.2 For vector interrupts, the address of the subroutine is already known to the
microprocessor while for non-vectored interrupts, the device will have to supply the
address of the subroutine to the microprocessor.
1.3 They are TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

7. 2. Instruction cycle is defined, as the time required completing the execution
of an instruction. Machine cycle is defined as the time required completing one
operation of accessing memory, I/O or acknowledging an external request. T-cycle
is defined as one subdivision of the operation performed in one clock period
-------------------------------wai kit,teck you, kai jye, izzati, azlin----------------------
1. How many interrupts in 8085 microprocessor? Explain each one of them. List out the priority of the interrupts. Besides
that, What is the difference between vector and non vector interrupts?
Answer:
The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one
instruction, usually one of these instructions:
 One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to
memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
 CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and
third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 002Ch (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 0034h (hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into
stack and branches to 003Ch (hexadecimal) address.
Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register
into stack and branches to 0024h (hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts
can be enabled or disabled individually using SIM instruction.
The priority from highest to lowest; TRAP, RST7.5, RST6.5, RST5.5, and INTR.
When a processor is interrupted to do a particular task,Program counter should be loaded with the the address of
subroutine(task).If the processor automatically generates the address then it is known as vectored interrupt. If user has
to provide address of subroutine using CALL instruction then it is known as non vectored interrupt
2. Write an Assembly Language program that will delay the program for 1.8sec. Given system clock = 1M Hz. Round
answer to one decimal place.
ANSWER:
DELAY:
MVI B, 2
LOOP2:LXI C, FFFFH
LOOP1:DCR C
JNZ LOOP1
DCR B
JNZ LOOP2
RET
LOOP1 time delay =7+65534(4+10)+4+7=917494us

8. Total time delay = 7+(917494+4+10)+(917494+4+7)=1835020us
_________________________________________________________________________
1. a. Name the interrupt that has the highest priority and its call location.
Answer: TRAP, XX24H
b. EI
MVI A, 00011010B
SIM
From the instruction above, can you determine which interrupt/interrupts is/are enabled?
Answer: RST 5.5 only. RST 7.5 are not enabled due to bit D4=1. If bit D4=1, RST 7.5 flip-flop is reset OFF.
c. Name all of the software interrupts in 8085.
Answer: RST 0,RST 1,RST 2,RST 3,RST 4,RST 5,RST 6,RST 7
d. What is the RST for TRAP?
Answer: RST 4.5 is known as TRAP
2.
1. Explain the difference between a nonmaskable and maskable interrupt
Ans: maskable: the microprocessor can ignore or delay a maskable interrupt request if it is
performing some critical task.
Nonmaskable: the microprocessor has to respond to a nonmaskable request immediately.
1. List the 8085 vectored interrupts, nonmaskable interrupt and their vectored memory locations.
Ans: RST7.5 maskable 003C RST6.5
maskable 0034 RST5.5 maskable 002C
TRAP nonmaskable 0024
1. List the interrupt(s) that is/are:
i. level sensitive only Ans: RST5.5, RST6.5 ii. edge sensitive
only RST7.5
iii. both level and edge sensitive TRAP
1. How long can the INTR pulse stay high?
Ans: The INTR pulse can remain high until the interrupt flip-flop is set by the EI instruction in the service routine. If
it remains high after the execution of the EI instruction, the processor will be interrupted again, as if it were a new
interrupt.
1) PUSH PSW
PUSH A
PUSH B
CMA
ANI 10011111B
POP (1)
POP (2)
POP (3)
What should be filled into the boxes 1, 2 and 3?
Ans: 1) B, 2) A, 3) PSW

9. 2) MVI A, 10101010B
STA 3000H
LXI H, 3000H
DCR M
LDA 3000H
What is the value of register Accumulator?
Ans: 10101010B
-------------------------------------------------------------------------------------------------------------------
1. Illustrate the data input from the DIP switches ?
Ans :
- description tr state octal buffer
- 3 – to – 8 decoder
Interfacing circuit
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 = 84H
Multiple port Adress line A3 and A4 maybe 0 or 1
Instruction to read Input Port :
- To read the instruction from the input port, the instruction in 84H is used. When the instruction is executed, during
the M3 cycle, the 8085 places the address 84H on the low – order bus.
2. Explain the concept of memory mapped I/0 ?
Ans :
- The input and output device are identified by 16-bit address.
- Uses memory related instruction and control signals
- Instead of memory register, if an output devices is connected at the address, the accumulator contents will be
transferred to the output device. This is called memory mapped I/O.
Execution of memory related data transfer instructions
- Decoded the address bus to generate the device address pulse.
- AND the control signal.
- Use the device select pulse to enable the I/O.
----------------------------------------------------------------------------------------------------------------------
1.Which interrupt in the 8085 microprocessor has memory?
• The RST 7.5 interrupt is the only 8085 interrupt that has memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal.
– When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed
the interrupt signal.
– This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt.
2. Explain the purpose of the I/O instruction IN and OUT
Answer:
The IN instruction is used to move data from an I/O port into the accumulator.
The OUT instruction is used to move data from the accumulator into I/O port.
The IN and OUT instruction are used only on microprocessor, which use a separate address space for
interfacing.