Cache based side_channel_attacks Anestis Bechtsoudis

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New Cache Designs for Thwarting
Software Cache-based Side Channel
Attacks - Z. Wang & R. B. Lee
Anestis Bechtsoudis
mpechtsoud@ceid.upatras.gr
Patra 2010

2. Cache Based Side Channel Attacks
Contents
1
Introduction
2
Threat Model and Attacks
3
Proposed Models
4
Evaluation
5
Conclusions
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3. Cache Based Side Channel Attacks
1.
Introduction
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4. Cache Based Side Channel Attacks
Introduction 1/4
 Information intensive society – imperative
need for security
 Design of cryptographic systems to ensure
the data protection
 Extensive test to cryptosystems over time
 Cryptanalysis: the study of techniques to
reveal the secret parameters of a security
system
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5. Cache Based Side Channel Attacks
Introduction 2/4
 Classical cryptanalysis approach
 Weaknesses in the algorithm – mathematical model
 Attacks based on: ciphertext-only, known plaintext,
chosen plaintext/ciphertext …
 Black box approach of the cryptosystem
 The cryptographic primitive is actually
implemented in hardware
 Modern cryptanalysis: attacker knows much
more for the device – side channel leakage
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6. Cache Based Side Channel Attacks
Introduction 3/4
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7. Cache Based Side Channel Attacks
Introduction 4/4
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8. Cache Based Side Channel Attacks
2.
Threat Model and Attacks
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9. Cache Based Side Channel Attacks
Threat Model and Attacks 1/6
 Goal of the adversary is to learn information
that he has no legitimate access to
 Adversary: one or more unprivileged user
processes, including remote clients, in the
server where the secrets are processed
 No physical access to the device
 Goal achieved by performing legitimate
operations – normal process
 Victim and adversary are isolated processes
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10. Cache Based Side Channel Attacks
Threat Model and Attacks 2/6
Percival’s attack on OpenSSL implementation
of RSA algorithm in a SMT CPU
 RSA core operation: modulo exponentiation –
implemented with a series of ^2 and *
 The encryption key is divided into segments
 For each *, a multiplier is selected from precomputed constants stored in a LUT
 Segment of key is used to index the LUT
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11. Cache Based Side Channel Attacks
Threat Model and Attacks 3/6
 Attacker manages to run simultaneously
 Attack process sequentially and repeatedly
accesses an array, thus loading data to
occupy all cache lines
 At the same time he measures the delay for
each access to detect cache misses (ex. rdtsc
timer in intel x86)
 Victim’s cache accesses evict attacker’s data,
enabling detection from the attacker
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12. Cache Based Side Channel Attacks
Threat Model and Attacks 4/6
Cache
RAM
RSA
Attacker
 The attacker can identify which table entry is
accessed -> the index used -> segment of
the key
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13. Cache Based Side Channel Attacks
Threat Model and Attacks 5/6
Bernstein’s Attack on AES
 AES - “Black Box” software module
 Give inputs and measure computation time
 The execution time is input dependant and
can be exploited to recover secret key
 Attack consists of three phases: Learning,
Attacking and Key Recovery
 Statistical correlation analysis
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14. Cache Based Side Channel Attacks
Threat Model and Attacks 6/6
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15. Cache Based Side Channel Attacks
3.
Proposed Models
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16. Cache Based Side Channel Attacks
Proposed Models 1/4
 Problem -> Directly or indirectly cache
interference
 Learn from attacks and rewrite software
 Solutions are attack specific and performance
degradation (2x, 4x slower)
 Authors attempt to eliminate the root cause
with minimum impact and low cost
 Ideas -> Partitioning - Randomization
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17. Cache Based Side Channel Attacks
Proposed Models 2/4
Partition-Locked Cache (PLCache)
L
ID
Original Cache Line
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18. Cache Based Side Channel Attacks
Proposed Models 3/4
Random Permutation Cache (RPCache)
 Introduce randomization factor – no useful
information about which cache lines evicted
 Memory-to-cache mappings
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19. Cache Based Side Channel Attacks
Proposed Models 4/4
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20. Cache Based Side Channel Attacks
4.
Evaluation
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21. Cache Based Side Channel Attacks
Evaluation 1/
 OpenSSL 0.9.7a AES implementation
 Traditional cache, L1 PLCache and L1 RPCache
 5KByte AES protected data
 L2 large enough – no performance impact
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22. Cache Based Side Channel Attacks
Evaluation 1/
 PLCache & RPCache implemented in M-Sim v2.0
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23. Cache Based Side Channel Attacks
5.
Conclusions
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24. Cache Based Side Channel Attacks
Conclusions
 Cache-based side channel attacks can harm
general purpose cache based systems
 Software solution -> attack specific
 Hardware solutions -> general purpose
 PLCache: minimal hardware cost – software
developer must use different API
 RPCache: area & complexity in hardware – no
special treatment from software developers
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25. LOGO
Anestis Bechtsoudis
mpechtsoud@ceid.upatras.gr
Patra 2010