The document discusses Bluespec, a hardware description language that combines features of Haskell and SystemVerilog assertions (SVA). Bluespec models all state explicitly using guarded atomic actions on state. Behavior is expressed as rules with guards and actions. Assertions in Bluespec are compiled into finite state machines and checked concurrently as rules. The document provides an example of using Bluespec to write functional and performance assertions for a cache controller design.

1. Synthesis of Synchronous Assertions with Guarded Atomic Actions MIT && Bluespec, Inc. guys Presented by: Suman Karumuri Andy Bartholomew

2. Life Cycle of a chip

8. Blue spec

10. Bluespec -> Chip Extended Haskell TRS Verilog Or C RTL Synthesis Concurrency and atomicity Correct Programs TRS: Term Rewriting system RTL: Register transfer language.

15. Summary: Bluespec All state (e.g., Registers, FIFOs, RAMs, ...) is explicit. Behavior is expressed in terms of guarded atomic actions on the state: Rule: condition  action Rules can manipulate state in other modules only via their interfaces. interface module

17. Compiler model Compiler generates a scheduler to pick a non-conflicting subset of “ready” rules Muxing for each state element  1  n Modules (Current state) Modules (Next state) Rules      n  n guard action Scheduler  1  n  1  n “ CAN_FIRE” “ WILL_FIRE”

18. SVA + Blue spec = BSV

26. Bluespec System Verilog(BSV)

35. Other combinations

39. General model of an assertion

41. Case study

51. Questions?

52. BSV code compliation function Vector#(64, Complex) ifft (Vector#(64, Complex) in_data); //Declare vectors Vector#(4,Vector#(64, Complex)) stage_data; stage_data[0] = in_data; for (Integer stage = 0; stage < 3; stage = stage + 1) stage_data[stage+1] = stage_f (stage,stage_data[stage]); return (stage_data[3]); Stage_f can be inlined now. But the number of transistors has tripled. stage_data[1] = stage_f (0,stage_data[0]); stage_data[2] = stage_f (1,stage_data[1]); stage_data[3] = stage_f (2,stage_data[2]);

54. 802.11a Transmitter Synthesis results (Only the IFFT block is changing) TSMC .18 micron; numbers reported are before place and route. All these designs were done in less than 24 hours! 1.0 MHz 04 4.91 Combinational 12 MHZ 6.0 MHz 3.0 MHz 1.5 MHz 1.0 MHz 1.0 MHz Min. Freq Required 48 24 12 06 04 04 ThroughputLatency (CLKs/sym) 1.84 SF(2 Bfly-4s) 2.45 SF(4 Bfly-4s) 5.25 Pipelined 1.52 3.69 3.97 Area (mm 2 ) SF (1 Bfly4) Super-Folded (8 Bfly-4s) Folded (16 Bfly-4s) IFFT Design The same source code