Asic design lect 3

1. 1
Application Specific IntegratedApplication Specific Integrated
Circuits (ASIC)Circuits (ASIC)
IntroductionIntroduction
BEIT VII
KICSIT
Sep 4 2012 Lacture 3

2. 2
Chip Architecture or RoutingChip Architecture or Routing StyleStyle
Sep 4 2012 Lacture 3

3. 3
FPGA FeaturesFPGA Features
Common FPGA Features
•Configurable Logic Block (CLBs)
• Basic logic unit in an FPGA.
• Consists of a configurable switch matrix (LUT or MUX) with 4
or 6 inputs, some selection circuitry (MUX, etc), and flip-flops.
•Interconnect
• Flexible interconnect routing routes the signals between CLBs
and to and from I/Os.
•Select I/O (I/OBs)
• Dozens of I/O standards
• I/O in FPGAs is grouped in banks
• Each bank independently able to support different I/O standards
Sep 4 2012 Lacture 3

4. 4
FPGA FeaturesFPGA Features
Common FPGA Features
•Memory
• Embedded Block RAM memory is available in most
FPGAs.
• Allows for on-chip memory in your design.
• Xilinx FPGAs provide up to 10 Mbits of on-chip
memory in 36 kbit blocks.
• Support true dual-port operation.
Sep 4 2012 Lacture 3

5. 5
FPGA FeaturesFPGA Features
•Complete Clock Management
• Clock management in electronic designs is most
important.
• The system performance results in totally disrupted and
data loss, without proper Clock management .
• The most advanced FPGAs from Xilinx offer both digital
clock management and phase-looped locking that provide
precision clock synthesis combined with jitter reduction and
filtering.
Sep 4 2012 Lacture 3

6. 6
FPGA FeaturesFPGA Features
Sep 4 2012 Lacture 3

7. 7
FPGA FeaturesFPGA Features
•Up to > 1,000 I/O “pins” (several 100 MHz)
Sep 4 2012 Lacture 3

8. 8
ASIC Design ProcessASIC Design Process
S-1 Design Entry: Schematic entry
or HDL description
S-2: Logic Synthesis: Using
Verilog HDL or VHDL and
Synthesis tool, produce a netlist-
logic cells and their interconnect
detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip
S-6 Placement: Fix cell locations in
a block
S-7 Routing: Make the cell and
block interconnections
S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation
Sep 4 2012 Lacture 3

9. 9
Designing Logic with FPGAs
• High level Description of Logic Design
• Hardware Description Language (Textual)
• Compile (Synthesis) into NETLIST.
• Boolean Logic Gates.
• Target FPGA Device
• Mapping
• Routing
• Bit File for FPGA
• Commercial CAE Tools
(Complex & Expensive)
• Logic Simulation
•Design Flow
Sep 4 2012 Lacture 3

10. 10
Configuring an FPGA
• Millions of SRAM cells holding LUTs and
Interconnect Routing
• Volatile Memory. Lose configuration when
board power is turned off.
• Keep Bit Pattern describing the SRAM
cells in non-Volatile Memory e.g. PROM
or Digital Memory card
• Configuration takes ~ secs
•Programming
•Bit File
•JTAG
Sep 4 2012 Lacture 3

11. 11
Configuring an FPGA
Sep 4 2012
• Different requirements of system designers and various
methods for configuring Xilinx FPGAs, CPLDs, and
PROMs.
• Different configuration modes to assist the designer in
selecting an appropriate configuration method.
• Three general steps necessary to configure or program a
Xilinx programmable logic device:
Lacture 3

12. 12
Configuring an FPGA
Sep 4 2012
• Step 1 - Design Entry
• Software design entry tools are used to create a design in VHDL,
Verilog, ABEL or Schematic.
• Step 2 – Implementation
•Software implementation tools are used to fit the design netlist
into the desired Xilinx architecture and produce a configuration
bitstream.
Lacture 3

13. 13
Configuring an FPGA
Sep 4 2012
• Step 3 - Configuration or Programming
• Configuration is the process of downloading configuration data
into an FPGA using an external data source, such as a PROM,
CPLD, or microprocessor.
• Programming is the process of loading the configuration data or
program data into a CPLD or PROM.
Lacture 3

14. 14
JTAG – Overview
Sep 4 2012
• JTAG (Joint Test Action Group)
• Commonly-used name for IEEE std 1149.1,
which defines a method for testing board-level
interconnect - also called Boundary Scan.
• The JTAG standard was developed to provide a
simple way of testing circuit boards for bad
connections, shorted pins, open pins, bad traces,
etc.
• More recently, PLD vendors have made use of
JTAG as a convenient way of configuring devices.
Lacture 3

15. 15
JTAG – Overview
Sep 4 2012
• JTAG compliant devices have dedicated
hardware that comprises a state machine and
several registers.
• This dedicated hardware interprets instructions
and data provided by four dedicated signals.
• TDI (Test Data In)
• TDO (Test Data Out)
• TMS (Test Mode Select)
• TCK (Test Clock).
Lacture 3

16. 16
JTAG – Overview
Sep 4 2012
• The dedicated JTAG hardware interprets
instructions and data on the TDI and TMS
signals, and drives data out on the TDO
signal.
•The TCK signal is used to clock the
process.
Lacture 3

17. 17
JTAG – Overview
Sep 4 2012
• A single JTAG port can connect to one or
multiple JTAG compliant devices.
• With multiple devices, it is called a “JTAG
chain”
• The TMS and TCK are tied to all the devices
directly.
• TDI and TDO form a chain. TDO from one
device goes to TDI of the next one in the chain.
Lacture 3

18. 18
JTAG – Overview
Sep 4 2012
•The master controlling the chain (a
computer usually) closes the chain.
• Each device in the chain has an ID, so the
computer controlling the JTAG chain can
figure out which devices are present.
Lacture 3

19. 19
JTAG – Overview
Sep 4 2012 Lacture 3

20. 20
JTAG – Overview
Sep 4 2012 Lacture 3

21. 21
BSDL (Boundary Scan Description
Language) files :
Sep 4 2012
• Any manufacturer of a JTAG compliant
device must provide a BSDL file for that
device.
• The BSDL file contains information on the
function of each of the pins on the device -
which are used as I/Os, which are power or
ground, etc.
Lacture 3

22. 22
BSDL (Boundary Scan Description
Language) files :
Sep 4 2012
• All Xilinx BSDL files have a file extension
of .bsd.
• Other manufacturers may use different file
extensions.
• BSDL files for other manufacturers can
typically be found on the manufacturer's web
site.
Lacture 3

23. 23
Other Configuration modes of FPGA
Sep 4 2012
• Besides JTAG or Boundary Scan, other
configuration modes of FPGA:
• Master Serial Mode
• Slave Serial Mode
• SelectMap Mode
Lacture 3

24. 24
Master Serial Mode
Sep 4 2012
• The simplest mode
• FPGA loads configuration data from a serial PROM
• FPGA drives Configuration clock and provides all
of the control logic
• Data is loaded at one bit per CCLK
Lacture 3

25. 25
Slave Serial Mode
Sep 4 2012
• It involves the use of a transmission method and an
external clock
• External clock, a microprocessor, another FPGA or
a download cable are required.
• Data is loaded to the target FPGA at one bit per
CCLK
Lacture 3

26. 26
SelectMAP Mode
Sep 4 2012
• It provides for parallel reading and writing through
byte-wide ports
• External clock, a microprocessor, another FPGA or
a download cable are required
• Data is loaded to the target FPGA at one byte per
CCLK
Lacture 3