Easy Learn to Verilog HDL

VLSI DESIGN
Reference Material

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Preface
The India Semiconductor Association (ISA), an Indian semiconductor
industry organization, has briefed growth, trends and forecasts for the Indian
semiconductor market in collaboration with a U.S. consulting company Frost
& Sullivan.

The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor
Market Update."

According to the report, total semiconductor consumption in India (total value
of semiconductors used for devices marketed in India) was $2.69 billion
(USD) in 2006. The $2.69 billion represents 1.09% of the global
semiconductor market. Of the total semiconductor consumption in India,
consumption by local Indian set manufacturers accounted for $1.26 billion.

The overall Indian semiconductor consumption will grow at an average rate of
26.7% per year in 2006 through 2009. Based on the actual consumption in
2006, the overall Indian semiconductor consumption is forecast to be $5.49
billion in 2009. This represents 1.62% of the global semiconductor market in
2009.

Semiconductor consumption by local Indian set manufacturers is predicted to
increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion
in 2009.

This material is the result of the Verilog Course Team’s practical experience
both in Design/Verification and Training. Many of the examples illustrated
throughout the material are real designs models. With Verilog Course Team’s
training experience has led to step by step presentation, which addresses
common mistakes and hard-to-understand concepts in a way that eases
learning.

Verilog Course Team invites suggestion and feedbacks from both students and
faculty community to improve the quality, content and presentation of the
material.

VLSI DESIGN

UNIT-I CMOS TECHNOLOGY

1. An overview of silicon semiconductor technology 1
1.1 The Fabrication of a Semiconductor Device 1
1.1.2 Wafer Fabrication 2
1.1.3 Assembly 6
1.2 Basic CMOS Technology 8
1.2.1 A Basic n-well CMOS Process 9
1.2.2 A Basic p-well CMOS Process 13
1.2.3 Twin-Tub (Twin-Well) CMOS Process 13
1.2.4 Silicon On Insulator (SOI) Process 14
1.3 INTERCONNECT 18
1.3.1 Metal Interconnect 18
1.3.2 Polysilicon/Refractory Metal Interconnect 19
1.3.3 Local Interconnect 20
1.4 CIRCUIT ELEMENTS 21
1.4.1 Resistors 21
1.4.2 Capacitors 21
1.4.3 Electrically Alterable ROMs 23
1.4.4 Bipolar Transistors 24
1.4.5 LatchUp 26
1.4.5.1 The Physical Origin of Latchup 26
1.4.5.2 Latchup Triggering 28
1.4.6 Latchup Prevention 29
1.5. LAYOUT DESIGN RULES 30
1.5.1 Layer Representations 31
1.5.2 CMOS n-well Rules 32
1.5.3 Scribe Line 34

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VLSI DESIGN

1.5.4 SOI Rules 34
1.5.5 Layer Assignments 35
1.6 PHYSICAL DEISGN 35
1.6.1 Basic Concept 35
1.6.2 CAD Tools sets 37
1.6.3 Physical Design-The Inverter 38
1.6.4 Physical Design-The NOR 38
1.6.5 Physical Design-The NAND 39
1.7 DESIGN STRATEGIES 39
1.7.1 Structured Design Strategies 40
1.7.2 Hierarchy 40

UNIT 2 MOS TRANSISTOR THEORY
2 .1 NMOS ENHANCEMENT TRANSISTOR 41
2.2 PMOS ENHANCEMENT TRANSISTOR 45
2.3 THRESHOLD VOLTAGE 45
2 . 3 . 1 Threshold Voltage Equations 46
2.4 BODY EFFECT 48
2.5 MOS Device Design Equations 48
2.5.1 Basic DC Equations 48
2.5.2 Second Order Effects 50
2.5.2.1 Threshold Voltage-Body Effect 51
2.5.2.2 Subthreshold Region 51
2.5.2.3 Channel-length Modulation 52
2.5.2.4 Mobility Variation 52
2.6 MOS MODELS 53
2.7 SMALL SIGNAL AC CHARACTERISTICS 54


VLSI DESIGN

2.8THE COMPLEMENTARY CMOS INVERTER –
DC CHARACTERISTICS 55
2.8.1 βn/βp ratio 61
2.8.2 Noise Margin 62
2.9 THE TRANSMISSION GATE 64
2.10 THE TRISTATE INVERTER 68

UNIT 3 SPECIFIFCATION OF VERILOG HDL
3. HISTORY OF VERILOG 69
3.1 BASIC CONCEPTS 69
3.1.1 Hardware Description Language 69
3.1.2 VERILOG Introduction 69
3.1.3 VERILOG Features 70
3.1.4 Design Flow 70
3.1.5 Design Hierarchies 73
3.1.5.1 Bottom up Design 73
3.1.5.2 Top-Down Design 74
3.1.6 Lexical Conventions 74
3.1.6.1 Whitespace 75
3.1.6.2 Comments 75
3.1.6.3 Identifiers and Keywords 76
3.1.6.4 Escaped Identifiers 76
3.1.7 Numbers in Verilog 76
3.1.7.1 Integer Numbers 77
3.1.7.2 Real Numbers 77
3.1.7.3 Signed and Unsigned Numbers 77
3.1.8 Strings 78
3.1.9 Data types 79


VLSI DESIGN

3.1.9.1 Data Types Value set 79
3.1.9.2 Nets 79
3.1.9.3 Vectors 80
3.1.9.4 Integer, Real and Time Register Data Types 80
3.1.9.5 Arrays 81
3.1.9.6 Memories 82
3.1.9.7 Parameters 82
3.1.9.8 Strings 82
3.2 MODULES 83
3.2.1 Instances 84
3.3 PORTS 84
3.3.1 Port Declaration 85
3.3.2 Port Connection Rules 85
3.3.3 Ports Connection to External Signals 86
3.4 GATE DELAYS 87
3.4.1 Rise, Fall, and Turn-off Delays 87
3.4.2 Min/Typ/Max Values 88
3.5 MODELING CONCEPTS 89
3.6 SWITCH LEVEL MODELING 90
3.6.1 Switch level primitives 91
3.6.2 MOS switches 92
3.6.3 CMOS Switches 93
3.6.4 Bidirectional Switches 94
3.6.5Power and Ground 95
3.6.6 Resistive Switches 95
3.8 Delay Specification on Switches 96
3.8.1 MOS and CMOS switches 96
3.8.2 Bidirectional pass switches 97

VLSI DESIGN

3.9 GATE LEVEL MODELING 101
3.9.1 Gate Types 101
3.10 BEHAVIORAL AND RTL MODELING 108
3.10.1 Operators 108
3.10.1.1 Arithmetic Operators 108
3.10.1.2 Relational Operators 109
3.10.1.3 Bit-wise Operators 110
3.10.1.4 Logical Operators 112
3.10.1.5 Reduction Operators 113
3.10.1.6 Shift Operators 114
3.10.1.7 Concatenation Operator 115
3.10.1.8 Replication Operator 116
3.10.1.9 Conditional Operator 116
3.10.1.10 Equality Operators 117
3.10.2 Operator Precedence 119
3.10.3 Timing controls 119
3.10.3.1 Delay-based timing control 119
3.10.3.2 Event based timing control 122
3.10.3.3 Level-Sensitive Timing Control 124
3.10.4 Procedural Blocks 124
3.10.5 Procedural Assignment Statements 125
3.10.6 Procedural Assignment Groups 126
3.10.7 Sequential Statement Groups 128
3.10.8 Parallel Statement Groups 128
3.10.9 Blocking and Nonblocking assignment 129
3.10.10 assign and deassign 130
3.10.11 force and release 131
3.10.12 Conditional Statements 131

VLSI DESIGN

3.10.12.1 The Conditional Statement if-else 131
3.10.12.2 The Case Statement 132
3.10.12.3 The casez and casex statement 134
3.10.13 Looping Statements 136
3.10.13.1 The forever statement 136
3.10.13.2 The repeat statement 136
3.10.13.3 The while loop statement 137
3.10.13.4 The for loop statement 138
3.11 DATA FLOW MODELING AND RTL 139
3.11.1 Continuous Assignment Statements 139
3.11.2 Propagation Delay 141
3.12 STRUCTURAL GATE LEVEL DESCRIPTION 141
3.12.1 2 to 4 Decoder 141
3.12.2 Comparator 142
3.12.3 Priority Encoder 144
3.12.4 D-latch 144
3.12.5 D Flip Flop 145
3.12.6 Half adder 145
3.12.7 Full adder 146
3.12.8 Ripple Carry Adder 146
UNIT 4 CMOS CHIP DESIGN
4.1 INTRODUCTION TO CMOS 148
4.2 LOGIC DESIGN WITH CMOS 149
4.2.1 COMBITIONAL LOGIC 149
4.2.2 INVERTER 150
4.2.3 The NAND Gate 151
4.2.4 The NOR Gate 152


VLSI DESIGN

4.3 TRANSMISSION GATES 153
4.3.1Multiplexers 153
4.3.2 Lathes 153
4.4 CMOS CHIP DESIGN OPTIONS 154
4.4.1 ASIC 154
4.4.2 Uses of ASICs 155
4.4.3 Full Custom ASICs 155
4.4.5 Semi-Custom ASICs 156
4.4.6 Standard- Cell-Based ASIC 156
4.4.7 Gate Array Asic 157
4.4.8 Channeled Gate Array 158
4.4.9 Channelless Gate Array 158
4.4.10 Structured Gate Array 159
4.5 PROGRAMMABLE LOGIC 159
4.5.1 Programmable Logic Structures 160
4.5.2 Programmable of PALs 161
4.5.3 Fusible Links 161
4.5.4 UV-erasable EPROM 161
4.5.5 EEPROM 161
4.5.6 Programmable Interconnect 162
4.6 ASIC DESIGN FLOW 163

UNIT-5 CMOS TEST METHODS
5.1 THE NEED FOR TESTING 165
5.1.1 Functionality Tests 166
5.2 MANUFACTURING TEST PRINCIPLS 166
5.2.1 FAULT MODELS 167
5.2.1.1 Stuck-At-Faults 167


VLSI DESIGN
5.2.1.2 Short-Circuit and Open-Circuit Faults 168
5.2.2 Observability 170
5.2.3 Controllability 171
5.2.4 Fault Coverage 171
5.2.5 Automatic Test Pattern Generation (Atpg) 171
5.2.6 Fault Grading And Fault Simulation 177
5.2.7 Delay Fault Testing 178
5.2.8 Statistical Fault Analysis 179
5.2.9 Fault Sampling 180
5.3 DESIGN STRATEGIES FOR TEST 180
5.3.1 Design for Testability 180
5.3.2 Ad-Hoc Testing 181
5.3.3 Scan-Based Test Techniques 184
5.3.3.1 Level Sensitive Scan Design (LSSD) 185
5.3.3.2 Serial Scan 187
5.3.3.3 Partial Serial Scan 188
5.3.3.4 Parallel Scan 190
5.3.4 Self-Test Techniques 191
5.3.4.1 Signature Analysis and BILBO 191
5.3.4.2 Memory Self-Test 193
5.3.4.3 Iterative logic array testing 194
5.3.5 IDDQ testing 194
5.4 CHIP-LEVEL TEST TECHNIQUES 194
5.4.1 Regular Logic Array 194
5.4.2 Memories 195
5.4.3 Random Logic 196
5.5 SYSTEM-LEVEL TEST TECHNIQUES 196
5.5.1 Boundary Scan 196


VLSI DESIGN
5.5.1.1 Introduction 196
5.5.1.2 The Test Access Port (TAP) 197
5.5.1.3 The Test Architecture 197
5.5.1.4 The TAP controller 198
5.5.1.5 The Instruction Register (IR) 198
5.5.1.6 Test-Data Registers 199
5.5.1.7 Boundary Scan Registers 199


VLSI DESIGN CMOS TECHNOLOGY
UNIT-I
An overview of silicon semiconductor technology
Silicon in its pure or intrinsic state is a semiconductor, having a bulk electrical
resistance somewhere between that of a conductor and an insulator. The
conductivity of silicon can be varied over several orders of magnitude by
introducing impurity atoms onto silicon crystal lattice. These dopants may either
supply free electrons or holes. Impurity elements that use electrons are referred to
as acceptors, since they accept some of the electrons already in the silicon,
leaving vacancies or holes. Similarly, donor elements provide electrons. Silicon
that contains a majority of donors is known as n-type and that which contains a
majority are brought together, the region where the silicon changes from n-type
and p-type materials are brought together, the region where the silicon changes
from n-type to p-type is called a junction. By arranging junctions in certain
physical structures and combining these with other physical structures, various
semiconductor devices may be constructed. Over the years, silicon semiconductor
processing has evolved sophisticated techniques for building these junctions and
other structures having special properties.
An integrated circuit is a small but sophisticated device implementing several
electronic functions. It is made up of two major parts: a tiny and very fragile
silicon chip (die) and a package which is intended to protect the internal silicon
chip and to provide users with a practical way of handling the component. The
various steps in manufacturing processes of transistor both in “front-end” and
“back-end” is taken as example, because it uses the MOS technology. Actually,
this technology is used for the majority of the ICs manufacturing companies.
1.1 The Fabrication of a Semiconductor Device
The manufacturing phase of an integrated circuit can be divided into two steps.
The first, wafer fabrication, is the extremely sophisticated and intricate process of
manufacturing the silicon chip. The second, assembly, is the highly precise and
automated process of packaging the die. Those two phases are commonly known
as “Front-End” and “Back-
end”. They include two test steps:
• Wafer probing and Final test.

The flow chart is shown in figure 1.1.

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Figure 1.1 Manufacturing Flow Chart of an Integrated Circuit
1.1.2 Wafer Fabrication (Front-End)
Identical integrated circuits, called die, are made on each wafer in a multi-step
process. Each
step adds a new layer to the wafer or modifies the existing one. These layers form
the elements of the individual electronic circuits. The main steps for the
fabrication of a die are summarized in the following table. Some of them are
repeated several times at different stages of the process. The order given here
doesn't reflect the real order of fabrication process.

This step shapes the different components. The
principle is quite simple (see drawing on next page).
PhotoMasking Resin is put down on the wafer which is then exposed
to light through a specific mask. The lighten part of
the resin softens and is rinsed off with solvents
(developing step).

This operation removes a thin film material. There are
Etching two different methods: wet (using a liquid or soluble
compound) or dry (using a gaseous compound like
oxygen or chlorine).

This step is used to introduce dopants inside the
Diffusion material or to grow a thin oxide layer onto the wafer.
Wafers are inserted into a high temperature furnace
(up to 1200 ° C) and doping gazes penetrate the
silicon or react with it to grow a silicon oxide layer.



Ionic It allows to introduce a dopant at a given depth into
Implantation the material using a high energy electron beam.

It allows the realization of electrical connections
Metal between the different cells of the integrated circuit
Deposition and the outside. Two different methods are used to
deposit the metal: evaporation or sputtering.

Wafers are sealed with a passivation layer to prevent
Passivation the device from contamination or moisture attack.
This layer is usually made of silicon nitride or a
silicon oxide composite.

It’s the last step of wafer fabrication. Wafer thickness
Back-lap is reduced (for microcontroller chips, thickness is
reduced from 650 to 380 microns), and sometimes a
thin gold layer is deposited on the back of the wafer.

Initially, the silicon chip forms part of a very thin (usually 650 microns), round
silicon slice: the raw wafer. Wafer diameters are typically 125, 150 or 200 mm (5,
6 or 8 inches). However raw pure silicon has a main electrical property: it is an
isolating material. So some of the features of silicon have to be altered, by means
of well controlled processes. This is obtained by "doping" the silicon.
Dopants (or doping atoms) are purposely inserted in the silicon lattice, hence
changing the features of the material in predefined areas: they are divided into
“N” and “P” categories representing the negative and positive carriers they hold.
Many different dopants are used to achieve these desired features: Phosphorous,
Arsenic (N type) and Boron (P type) are the most frequently used ones.
Semiconductors manufacturers purchase wafers predoped with N or P impurities
to an impurity level of.1 ppm (one doping atom per ten million atoms of silicon).
There are two ways to dope the silicon. The first one is to insert the wafer into a
furnace. Doping gases are then introduced which impregnate the silicon surface.
This is one part of the manufacturing process called diffusion (the other part being
the oxide growth). The second way to dope the silicon is called ionic
implantation. In this case, doping atoms are introduced inside the silicon using an
electron beam. Unlike diffusion, ionic implantation allows to put atoms at a given
depth inside the silicon and basically allows a better control of all the main


parameters during the process. Ionic implantation process is simpler than
diffusion process but more costly (ionic implanters are very expensive machines).

Figure 1.2 Diffusion and Ionic Implantation Processes
PhotoMasking (or masking) is an operation that is repeated many times during
the process. This operation is described in figure 1.3. This step is called
photomasking because the wafer is “masked” in some areas (using a specific
pattern), in the same way one “masks out” or protects the windscreens of a car
before painting the body. But even if the process is somewhat similar to the
painting of a car body, in the case of a silicon chip the dimensions are measured
in tenth of microns. The photoresist will replicate this pattern on the wafer. The
exposed part of the photoresist is then rinsed off with a solvent (usually
hydrofluoric or phosphoric acid).

Figure 1.3 Photo Masking Process
Metal deposition is used to put down a metal layer on the wafer surface. There
are two ways to do that. The process shown in the figure 1.4, is called sputtering.
It consists first in creating a plasma with argon ions. These ions bump into the
target surface (composed of a metal, usually aluminium) and rip metal atoms from
the target. Then, atoms are projected in all the directions and most of them
condense on the substrate surface.



Figure 1.4 Metal Deposition Process
Etching process is used to etch into a specific layer the circuit pattern that has
been defined during the photomasking process. Etching process usually occurs
after deposition of the layer that has to be etched. For instance, the poly gates of a
transistor are obtained by etching the poly layer. A second example is the
aluminium connections obtained after etching of the aluminum layer.

Figure 1.5 Etching Process
Photomasking, ionic implantation, diffusion, metal deposition, and etching
processes are repeated many times, using different materials and dopants at
different temperatures in order to achieve all the operations needed to produce the
requested characteristics of the silicon chip. The resolution limit (minimal line
size inside the circuit) of current technology is 0.35 microns. Achieving such
results requires very sophisticated processes as well as superior quality levels.
Backlap is the final step of wafer fabrication. The wafer thickness is reduced
from 650 microns to a minimum of 180 microns (for smartcard products).
Wafer fabrication takes place in an extremely clean environment, where air
cleanliness is one million times better than the air we normally breathe in a city,
or some orders of magnitude better than the air in a heart transplant operating
theatre. Photomasking, for example, takes place in rooms where there’s maximum


one particle whose diameter is superior to 0.5 micron (and doesn’t exceed 1
micron) inside one cubic foot of air.
All these processes are part of the manufacturing phase of the chip itself. Silicon
chips are grouped on a silicon wafer (in the same way postage stamps are printed
on a single sheet of paper) before being separated from each other at the
beginning of the assembly phase.
Wafer Probing. This step takes place between wafer fabrication and assembly. It
verifies the functionality of the device performing thousands of electrical tests, by
means of special microprobes. Wafer probing is composed of two different tests:
1. Process parametric test: This test is performed on some test samples and
checks the wafer fabrication process itself.
2. Full wafer probing test: This test verifies the functionality of the finished
product and is performed on all the dies. The bad dies are automatically marked
with a black dot so they can be separated from good die after the wafer is cut. A
record of what went wrong with the non-working die is closely examined by
failure analysis engineers to determine where the problem occurred so that may be
corrected. The percentage of good die on an individual wafer is called its yield.

Figure 1.6 Description of the Wafer Probing Operation

1.1.3 Assembly (Back-End)

Figure 1.7


The first step of assembly is to separate the silicon chips: this step is called die
cutting (figure 1.7). Then, the dies are placed on a lead frame: the “leads” are the
chip legs (which will be soldered or placed in a socket on a printed circuit board.
On a surface smaller than a baby's fingernail we now have thousands (or millions)
of electronic components, all of them interconnected and capable of implementing
a subset of a complex electronic function. At this stage the device is completely
functional, but it would be impossible to use it without some sort of supporting
system. Any scratch would alter its behavior (or impact its reliability), any shock
would cause failure. Therefore, the die must be put into a ceramic or plastic
package to be protected from the external world.

Figure 1.8 Description of The Assembly Process

Figure 1.9 Wire Bonding
Wires thinner than a human hair (for microcontrollers the typical value is 33
microns) are required to connect chips to the external world and enable electronic
signals to be fed through the chip. The process of connecting these thin wires
from the chip’s bond pads to the package lead is called wire bonding.
The chip is then mounted in a ceramic or plastic package. The package not only
protects the chip from external shocks, but also makes the whole device easier to
handle. These packages come in a variety of shapes and sizes depending on the
die itself and the application in which it will be used.



Figure 1.10 Wire Bonding Operation
Products are then marked with a “traceability code” which is used by the
manufacturer and the user to identify the function of the device (and its date of
fabrication). At the end of the assembly process, the integrated circuit is tested by
automated test equipment. Only the integrated circuits that passed the tests will be
packed and shipped to their final destination.

Figure 1.11 Different Kinds of Plastic Packages
1.2 Basic CMOS Technology
Complementary metal–oxide–semiconductor (CMOS) (pronounced "see-
moss), is a major class of integrated circuits. CMOS technology is used in
microprocessors, microcontrollers, static RAM, and other digital logic circuits.
CMOS technology is also used for a wide variety of analog circuits such as image
sensors, data converters, and highly integrated transceivers for many types of
communication. Frank Wanlass got a patent on CMOS in 1967 (US Patent
3,356,858).


CMOS is also sometimes referred to as complementary-symmetry metal–
oxide–semiconductor. The words "complementary-symmetry" refer to the fact
that the typical digital design style with CMOS uses complementary and
symmetrical pairs of p-type and n-type metal oxide semiconductor field effect
transistors (MOSFETs) for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low
static power consumption. Significant power is only drawn when the transistors in
the CMOS device are switching between on and off states. Consequently, CMOS
devices do not produce as much waste heat as other forms of logic, for example
transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices
without p-channel devices. CMOS also allows a high density of logic functions on
a chip.
The four main CMOS technologies are;
• n-well process.
• p-well process.
• twin-tub process.
• Silicon on insulator.
1.2.1 A Basic n-well CMOS Process
The basic process steps for pattern transfer through lithography, and having gone
through the fabrication procedure of a single n-type MOS transistor, the
generalized fabrication sequence of n-well CMOS integrated circuits, as shown in
figure. 1.12 In the following figures, some of the important process steps involved
in the fabrication of a CMOS inverter will be shown by a top view of the
lithographic masks and a cross-sectional view of the relevant areas. The n-well
CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer
is grown on the entire surface. The first lithographic mask defines the n-well
region. Donor atoms, usually phosphorus, are implanted through this window in
the oxide.

Figure 1.12


Once the n-well is created, the active areas of the nMOS and pMOS transistors
can be defined. Figures 1.13 through 1.18 illustrate the significant milestones that
occur during the fabrication process of a CMOS inverter.
Following the creation of the n-well region, a thick field oxide is grown in the
areas surrounding the transistor active regions, and a thin gate oxide is grown on
top of the active regions. The thickness and the quality of the gate oxide are two
of the most critical fabrication parameters, since they strongly affect the
operational characteristics of the MOS transistor, as well as its long-term
reliability.

Polysilicon Gate Connections
Figure 1.13
The polysilicon layer is deposited using chemical vapor deposition (CVD) and
patterned by dry (plasma) etching. CVD Chemical Reactions
• SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas)
• SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)
•

Figure 1.14



Isolation layer
Figure 1.15
The created polysilicon lines will function as the gate electrodes of the nMOS and
the pMOS transistors and their interconnects. Also, the polysilicon gates act as
self-aligned masks for the source and drain implantations that follow this step.
Using a set of two masks, the n+ and p+ regions are implanted into the substrate
and into the n- well, respectively. Also, the ohmic contacts to the substrate and to
the n-well are implanted in this process step.

Figure 1.16
An insulating silicon dioxide layer is deposited over the entire wafer using CVD.
Then, the contacts are defined and etched away to expose the silicon or
polysilicon contact windows. These contact windows are necessary to complete
the circuit interconnections using the metal layer, which is patterned in the next
step.

Figure 1.17


Metal (aluminum) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching.

Figure 1.18
Since the wafer surface is non-planar, the quality and the integrity of the metal
lines created in this step are very critical and are ultimately essential for circuit
reliability. The composite layout and the resulting cross-sectional view of the
chip, showing one nMOS and one pMOS transistor (built-in n-well), the
polysilicon and metal interconnections. The final step is to deposit the passivation
layer (for protection) over the chip, except for wire-bonding pad areas. The
patterning process by the use of a succession of masks and process steps is
conceptually summarized in Figure. 1.19. It is seen that a series of masking steps
must be sequentially performed for the desired patterns to be created on the wafer
surface. An example of the end result of this sequence is shown as a cross-section
on the right.

Figure 1.19

1.2.2 A Basic p-well CMOS Process
N-well processes have emerged in popularity in recent years. Prior to this p-well
process was one of the most commonly available forms of CMOS. Typical p-well
fabrication steps are similar to an n-well process, except that a p-well is
implemented rather than an n-well. The first masking step defines the p-well
regions. This is followed by a low-dose boron implant driven in by a high-
temperature step for the formation of the p-well. The well depth is optimized to
ensure against n-substrate to n+ diffusion breakdown, without compromising p-
well to p+ separation.
The next steps are to define the devices and other; to grow field oxide; contact
cuts; and metallization. A p-well mask is used to define the p-channel transistors
and Vss contacts. Alternatively, an n-plus mask to define the n-channel
transistors, because the masks usually are the complement of each other. P-well
process are preferred in circumstances where the characteristics of the n- and p-
transistors are required to be more balanced than that achievable in an n-well
process. Because the transistor that resides in the native substrate tends to have
better characteristics, the p-well process has better p devices than an n-well
process. Because p-devices inherently have lower gain than n-devices, the n-well
process exacerbates this difference while a p-well process moderates the
difference.
1.2.3 Twin-Tub (Twin-Well) CMOS Process
Twin-tub technology provides the basis for separate optimization of the nMOS
and pMOS transistors, thus making it possible for threshold voltage, body effect
and the channel transconductance of both types of transistors to be tuned
independently. Generally, the starting material is a n+ or p+ substrate, with a
lightly doped epitaxial layer on top. This epitaxial layer provides the actual
substrate on which the n-well and the p-well are formed.

Figure 1.20 Twin-well CMOS process cross section
Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the
desired device characteristics. The aim of epitaxy is to grow high-purity silicon


layers of controlled thickness with accurately determined dopant concentration
distributed homogenously throughout the layer.
The electrical properties of this layer are determined by the dopant and its
concentration in the silicon. The process sequence, which is similar to the n-well
process apart from the tub formation where both p-well and n-well are utilized,
entails the following steps,

• Tub formation.
• Thin-oxide construction.
• Source and drain implantations.
• Contact cut definition.
• Metallization.
In the conventional n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among
other effects, results in unbalanced drain parasitics. The twin-tub process (figure
1.20) also avoids this problem.
1.2.4 Silicon On Insulator (SOI) Process
Silicon on insulator technology (SOI) refers to the use of a layered silicon-
insulator-silicon substrate in place of conventional silicon substrates in
semiconductor manufacturing, especially microelectronics, to reduce parasitic
device capacitance and thereby improve performance. SOI-based devices differ
from conventional silicon-built devices in that the silicon junction is above an
electrical insulator, typically silicon dioxide or (less commonly) sapphire. The
choice of insulator depends largely on intended application, with sapphire being
used for radiation-sensitive applications and silicon oxide preferred for improved
performance and diminished short channel effects in microelectronics devices.
The insulating layer and topmost silicon layer also vary widely with application.

The first implementation of SOI was announced by IBM in August 1998. Rather
than using silicon as the substrate, the technologies have sought to use an
insulating substrate to improve process characteristics such as latchup and speed.
Hence the emergence of Silicon On Insulator (SOI) technologies. SOI CMOS
processes have several potential advantages over the traditional CMOS
technologies. These include closer packing of p- and n- transistors, absence of
latchup problems, and lower parasitics substrate capacitances. In the SOI process
a thin layer of single-crystal silicon film is epitaxially grown on an insulator such
as sapphire or magnesium aluminium spinal. Alternatively, the silicon may be
grown on SiO2 that has been in turn grown on silicon. This option has proved
more popular in recent years due to the compatibility of the starting material with
conventional silicon CMOS fabrication. Various masking and doping techniques


(figure 1.21) are then used to form p-channel and n-channel devices. Unlike the
more conventional CMOS approaches, the extra steps in well formation do not
exist in the technology.
The steps used in typical SOI CMOS process are as follows. A thin film (7-8 µm)
of very lightly –doped n-type Si is grown over an insulator, Sapphire or SiO2 is
commonly used insulator (figure 1.21 a).
• An anisotropic etch is used away the Si except where a diffusion area (n or p)
will be needed. The etch must be anisotropic since the thickness of the Si is much
greater than the spacing desired between the Si “islands: (figure 1.21 b, c).
• The p-islands are formed next by masking the n-islands with a photoresist. A
p-type dopant, boron, for example is then implanted. It is masked by the
photoresist, but forms p-islands at the unmasked islands. The p-islands will
become the n-channel devices (figure 1.12 d).
• The p-islands are then covered with a photoresist and an n-type dopant-
phosphorus, for example is implanted to form the n-islands. The n-islands will
become the p-channel devices (figure 1.12 e).
• A thin gate oxide (around 100-250 A) is grown over all of the Si structures,
this is normally done by thermal oxidation.
• A polysilicon film is deposited over the oxide. Often the polysilicon is doped
with phosphorus to reduce its resistivity (figure 1.12f).
• The polysilicon is then patterned by photomasking and is etched. This defines
the polysilicon layer in the structure (figure 1.12 g).
• The next step is to form the n-doped source and drain of the n-channel devices
in the p-islands. The n-islands are covered with a photoresist and an n-type
dopant, normally phosphorus is implanted. The dopant and an n-type dopant,
normally phosphorus is implanted. The dopant will be blocked at the n-islands by
the photoresist, and it will be blocked from the gate region of the p-islands by the
polysilicon. After this step the n-channel devices are complete (figure 1.12 h).
• The p-channel devices are formed next by masking the p-islands and
implanting a p-type dopant such as boron. The polysilicon over the gate of the n-
island will block the dopant from the gate, thus forming the p-channel devices
(figure 1.12 i).
• A layer of phosphorus glass or some other insulator such as silicon dioxide is
then deposited over the entire structure.
• The glass is etched as contact –cut locations. The metallization layer is formed
next by evaporating aluminum over the entire surface and etching it to leave only
the desired metal wires. The aluminium will flow through the contact cuts to
make contact with the diffusion or polysilicon regions (figure 1.12 j).
• A final passivation layer of phosphorus glass is deposited and etched over
bonding pad locations (not shown in figure).


Because the diffusion regions extend to the insulating substrate, only “sidewall”
areas associated with source and drain diffusion contribute to the parasitic
junction capacitance. Since sapphire and SiO2 are extremely good insulators,
leakage currents between transistors and substrate and adjacent devices are almost
eliminated.
In order to improve the yield, some processes use “preferential etch” in which he
island edges are tapered. Thus aluminium or poly runners can enter and leave the
islands with a minimum step height. This is contrasted to “fully anisotropic etch”
in which the undercut is brought to zero, as shown in figure 1.13.An” isotropic
etch” is also shown in the same diagram for the comparison.

Figure 1.12 SOI Process Flow


The advantages of SOI technology are as follows,

• Due to absence of wells, transistor structures denser than bulk silicon are
feasible. Also direct n-to-p connections may be made.
• Lower substrate capacitances provide the possibility for faster circuits.
• No field-inversion problems exist( insulating substrate)
• There is no latchup because of the isolation of the n-and p-transistors by the
insulating substrate.
• Because there is no conducting substrate, there are no body-effect problems.
However the absence of a backside substrate contact could lead to odd device
characteristic such as the “kink” effect in which the drain current increases
abruptly at around 2 to 3 volts.
Some of the disadvantages are,
• Due to absence of substrate diodes, the inputs are somewhat more difficult to
protect. Because device gains are lower, I/O structures have to be larger.
• Single crystal sapphire, spinel substrate, and silicon SiO2 are considerably
more expensive than silicon substrate and their processing techniques tend to be
less developed than bulk silicon techniques.

Figure 1.13 Classification of Etching processes


1.3 INTERCONNECT
The most important additions for CMOS logic processes are additional signal-
and power-routing layers. This eases the routing (especially automated
netting) of logic signals between modules and improves the power and clock
distribution to modules. Improved mutability is achieved through additional
layers of metal or by improving the existing polysilicon interconnection
layer.
1.3.1 Metal Interconnect
A second level of metal is almost mandatory for modern CMOS digital. A
third layer is becoming common and is certainly required for leading-edge
high-density, high-speed chips. Normally, aluminum is used for the metal
layers. I f some form of planarization is employed the second-level metal
pitch can be the same as the first. As the vertical topology becomes more
varied, the width and spacing of metal conductors has to increase so that
the conductors do not thin and hence break at vertical topology jumps (step
coverage).

Contacting the second-layer metal to the first-layer metal is achieved by a
via, as shown in figure 1.14. If further contact to diffusion or polysilicon is
required, a separation between the via and the contact cut is usually
required. This requires a first-level metal tab to bridge between metal2 and
the lower-l e v e l conductor. It is important to realize that in contemporary
processes first level metal must be involved in any contact to underlying
areas. A number of contact geometries are shown in figure 1.15.

Figure 1.14 Two-level metal process cross section
Processes usually require metal borders around the via on both levels of
metal although some process require none. Processes may have no
restrictions on the placement of via with respect to underlying layers


(figure 1.15a) or they may have to be placed inside (figure 1.15b) or
outside (figur e1.15c) the underlying polysilicon or diffusion areas.
Aggressive processes allow the stacking of vias on top of contacts, as
shown in figure 1.15 (d).

a

b

c

d

Figure 1.15 Two-level metal /via contact geometrics
Consistent with the relatively large thickness of the intermediate isolation
layer, the vias might be larger than contact cuts and second-layer metal
may need to be thicker and require a larger via overlap although modern
processes strive for uniform pitches on metal I and metal2.
The process steps for a two-metal process are briefly as follows:
• The oxide below the first-metal layer is deposited by atmospheric
chemical vapor deposition (CVD).
• The second oxide layer between the two metal layers is applied in a
similar manner.
• Depending on the process, removal of the oxide is accomplished using
a plasma etcher designed to have a high rate of vertical ion bombardment.
This allows fast and uniform etch rates. The structure of a via etched
using such a method is shown in figure1.14.
1.3.2 Polysilicon/Refractory Metal Interconnect
The polysilicon layer used for the gates of transistors is commonly used
as i t interconnect layer. However, the sheet resistance of doped
polysilicon is between 20Ω and 40Ω/square. If used as a long distance
conductor, a polysilicon wire can represent a significant delay.


One method to improve this that requires no extra mask levels is to
reduce the polysilicon resistance by combining it with a refractory metal.
Three such approaches are illustrated in figure 1.16.In figure 1.16(a)
a silicide (e.g., silicon and tantalum) is used as the gate material. Sheet
resistances of the order of 1 to 5Ω/square may be obtained. This is called
the, silicide gate approach.

Figure 1.16 Refractory metal interconnect
Silicides are mechanically strong and may be dry ached in plasma
reactors. Tantalum silicide is stable throughout standard processing and
has the advantage that it may be retrofitted into existing process lines.
Figure 1.16(b) uses a sandwich of silicide upon polysilicon, which is
commonly called the polycide approach. Finally, the silicide/polysilicon
approach may he extended to include the formation of source and d r a i n
r e g i o n s u s i n g t h e s i l i c i d e . This is called the salicide process (Self
Aligned SILICIDE) (figur e 1.16c). The effect of all of these processes
is to reduce the "second layer " interconnect resistance, allowing the gate
material to be used as a moderate long-distance interconnect. This is
achieved by minimum perturbation of an existing process. An increasing
trend in process is to use the salicide approach to reduce the resistance of
both gate and source/drain conductors.
1.3.3 Local Interconnect
The silicide itself may be used as a "local interconnect" layer for
connection within c e l ls . T i N i s u sed as a n example. Local
interconnect allows a direct connection between polysilicon and
diffusion, thus alleviating the need for area intensive contacts and metal.
Figure 1.17 shows a portion (p-devices only) of a six transistor SRAM
cell that uses local interconnect. The local interconnect has been used to
make the polysilicon-to-diffusion connections within the cell, thereby
alleviating the need to use metal (and contacts). Metal2 (not shown) bit
lines run over the cell vertically. Use of local i n t e r c o n n e c t in this RAM
reduced the cell area by 25%.



Figure 1.17 Local interconnect as used in a RAM cell
In general, local interconnect if available can be used to complete intracell
routing, leaving the remaining metal layers for global wiring.

1.4 CIRCUIT ELEMENTS
1.4.1 Resistors
Polysilicon, if left undoped, is highly resistive. This property is used to build
resistors that are used in static memory cells. The process step is achieved by
preventing the resistor areas from being implanted during normal
processing. Resistors in the tera-Ω (10 12 Ω) region are used. A value of
3TΩ results in a standby current of 2µA for a 1 Mbit memory.
For mixed signal CMOS (analog and digital), a resistive metal such as
nichrome may be added to produce high-value, high-quality resistors. The
resistor accuracy might be further improved by laser trimming the result
resistors on each chip to some predetermined test specification. In this
process a high-powered laser vaporizes areas of the metal resistor until it
meets a measurement constraint. Sheet resistance values in the KΩ/square
are normal. The resistors have excellent temperature stability and long-term
reliability.
1.4.2 Capacitors
Good quality capacitors are required for switched-capacitor analog circuits
while small high-value/area capacitors are required for dynamic memory
cells. Both types of capacitors are usually added by using at least one extra
layer of polysilicon, although the process techniques are very different.


Polysilicon capacitors for analog applications are the most straightforward.
A second thin-oxide layer is required in order to have an oxide sandwich
between the two polysilicon layers yielding a high-capacitance/unit area.
Figure 1.18 shows a typical polysilicon capacitor. The presence of this,
second oxide can also be used to fabricate transistors. These may differ,
characteristics from the primary gate oxide devices. For memory capacitors
recent processes have used three dimensions to increase the
capacitance/area.

Figure 1.18 Polysilicon Capacitor
One popular structure is the trench capacitor,
which has evolved considerably over the years to push memory densities to
64Mbits and beyond. A typical trench structure is shown in figure 1.19(a).
The sides of the trench are doped n+ and coated with a thin 1Onm oxide.
Sometimes oxynitride is used because its high dielectric constant increases
capacitance.

a

b

Figure 1.19 Dynamic memory capacitors
The trench is filled with a polysilicon plug, which forms the bottom plate of
the cell storage capacitor. This is held at VDD /2 via a metal connection at the


edge of the array. The sidewall n+ forms the other side of capacitor and one
side of the pass transistor that is used to enable data onto the bit lines. The
bottom of the trench has a p+ plug that forms a channel stop region to isolate
adjacent capacitors. The trench is 4µm deep and has a capacitance of 90fF.
Rather than building a trench, figure 1.19(b) shows a fintype- capacitor used
in a 64-Mb DRAM. The storage capacitance is 20 to 30 fF. The fins have the
additional advantage of reducing the bit capacitance by shielding the bit
lines. The fabrication of 3D-process structures such as these is a constant
reminder of the skill, perseverance, and ingenuity of the process engineer.

1.4.3 Electrically Alterable ROMs
Electrically alterable/erasable R O M ( E A R O M / E E P R O M ) i s added to
CMOS processes to yield permanent but reprogrammable s to r ag e to a
process. This is usually added by adding a polysilicon layer. Figure 1.20
shows a typical memory structure, which consists o f a stacked-gate
s t r u c t u r e . The normal gate is left floating, while a control gate is placed
above the floating gate. A very thin oxide called the tunnel oxide
separates the floating gate from the source, drain, and substrate.

Figure 1.20 EEPROM technology
This is usually 10 nm thick. Another thin oxide separates the control gate
from the floating gate. By controlling the control-gate, source, and drain
voltages, the thin tunnel oxide between the floating gate and the drain of
the device is used to allow electrons to "tunnel" to or from the floating
gate to turn the cell or on, respectively, using Fowler-Nordheim tunneling.
Alternatively, by setting the appropriate voltages on the terminals, "hot
electrons" can be induced to charge the floating gate, thereby
programming the transistor. In non-electrically alterable versions of the
technology, the p r o cess can be reversed by illuminating the gate with UV
light. In these the chips are usually housed in glass-lidded packages.


1.4.4 Bipolar Transistors
The addition of the bipolar transistor to the device repertoire forms the
basis for BiCMOS processes. Adding an npn-transistor can markedly aid in
reducing the delay times of highly loaded signals, such as memory word
lines microprocessor busses. Additionally, for analog applications bipolar
transistors may be used to provide better performance analog functions than
MOS alone. To get merged bipolar/CMOS functionality,

Figure 1.21 Typical mixed signal BiCMOS process cross section

Figure 1.22 BiCMOS process steps for the cross section shown in
figure 1.21


MOS transistors can add to a bipolar process or vice versa. In past days,
MOS processes always had to have excellent gate oxides while bipolar
processes had to have precisely controlled diffusions.
A BiCMOS process has to have both. A mixed signal BiCMOS process
cross section is shown in figure 1.21. This process features both npn- and
pnp-transistors in addition to pMOS and nMOS transistors. The major
processing steps are summarized in figure 1.22, showing the particular
device to which they correspond. The base layers of the process are similar
to the process shown in figure 1.12. The starting material is a lightly-
doped p-type substrate into which antimony or arsenic are diffused to
form an n+ buried layer. Boron is diffused to form a buried p + layer. An n-
type epitaxial layer 4.0 µm thick is then grown. N-wells and p-wells are then
diffused so that they join in the middle of the epitaxial layer. This
epitaxial layer isolates the pnp-transistor in the horizontal direction, while
the buried n+ layer isolates it vertically. The npn-transistor is junction-
isolated. The base for the pnp is then ion-implanted using phosphorous. A
diffusion step follows this to get the right doping profile. The npn-
collector is formed by depositing phosphorus before LOCOS. Field
oxidation is carried out and the gate oxide is grown. Boron is then used to
form the p-type base of the npn transistor.
Following the threshold adjustment of the pMOS transistors, the
polysilicon gates are defined. The emitters of the npn-transistors employ
polysilicon rather than a diffusion. These are formed by opening windows
and depositing polysilicon. The n+ and p+ source/drain implants are then
completed. This step also dopes the npn-emitter and the extrinsic bases of
the npn- and pnp-transistors (extrinsic because this is the part of the base
that is not directly between collector and emitter).

Following the deposition of PSG, the normal two-layer metallization steps
are completed. Representative of a high-density digital BiCMOS process
is that represented by the cross section shown in figure 1.23. The buried-
layer-epitaxial layer-well structure is very similar to the previous
structure. However because this is a 0.8µm process, LDD structures must
be constructed for the p-transistors and the n-transistors. The npn is formed
by a double-diffused sequence in which both base and emitter are formed
by impurities that diffuse out of a covering layer of polysilicon. This
process, intended for logic applications, has only an npn-transistor. The
collector of the npn is connected to the n-well, which is in turn connected
to the VDD supply. Thus all npn-collectors are commoned. A typical npn-
transistor with a 0.8µm-square emitter has a current gain of 90 and an ft. of
15 GHz.


Figure 1.23 Digital BiCMOS process cross section

1.4.5 LatchUp
If every silver lining has a cloud, then the cloud that has plagued CMOS is
a parasitic circuit effect called "latchup." The result of this effect is the
shorting of the VDD and Vss lines, usually resulting in chip self-
destruction or at least system failure with the requirement to power down.
This effect was a critical factor in the lack of acceptance of early CMOS
processes, but in cur-rent processes it is controlled by process innovations
and well-understood circuit techniques.
1.4.5.1 The Physical Origin of Latchup
The source of the latchup effect may be explained by examining the
process cross section of a CMOS inverter, shown in figure 1.24(a), on
which is overlaid an equivalent circuit. The schematic depicts, in addition
to the expected nMOS and pMOS transistors, a circuit composed of an
npn-transistor, a pnp-transistor, and two resistors connected between the
power and ground rails (figure 1.24b). Under the right conditions, this
parasitic circuit has the VI characteristic shown in figure 1.24(c), which
indicates that above some critical voltage (known as the trigger point) the
circuit "snaps" and draws a large current while maintaining a low voltage
across the terminals (known as the holding voltage). This is, in effect, a
short circuit. As mentioned, the bipolar devices and resistors shown in
figure 1.24 (b) are parasitic, that is an unwanted byproduct of producing
pMOS and nMOS transistors. From the figure 1.24(a) reveals how these
devices are constructed. The figure shows a cross-sectional view of a
typical (n-well) CMOS process. The (vertical) pnp-transistor has its
emitter formed by the p+ source/drain implant used in the pMOS
transistors. Note that either the drain or source may act as the emitter
although the source is the only terminal that can maintain the latchup
condition. The base is formed by the n-well, while the collector is the p-

substrate. The emitter of the (lateral) npn-transistor is the n+ source/drain
implant, while the base is the p-substrate and the collector is the n-well. In
addition, substrate resistance R substrate and well resistance R well are due to
the resistivity of the semiconductors involved.

Figure 1.24 The origin model, and VI characteristics of CMOS Latchup
Consider the circuit shown in figure 1.24(b). If a current is drawn from the
npn-emitter, the emitter voltage becomes negative with respect to the base until
the base emitter voltage is approximately 0.7 volts. At this point the npn-
transistor turns on and a current flows in the well resistor due to common emitter
current amplification. This raises the base emitter voltage of the pnp-
transistor, which turns on when the pnp Vbe = - 0 . 7 volts. This in turn
raises the npn base voltage causing a positive feedback condition, which
has the characteristic shown in figure 1.24(c). At a certain npn-base-
emitter voltage, called the trigger point, the emitter voltage suddenly
"snaps back" and enters a stable state called the ON state. This state will
persist as long as the voltage across the two transistors is greater than the
holding voltage shown in the figure. As the emitter of the npn is the
source/drains of the n-transistor, these terminals are now at roughly 4
volts. Thus there is about 1 volt across the CMOS inverter, which will


most likely cause it to cease operating correctly. The current drawn is
usually destructive to metal lines supplying the latched up circuitry.
1.4.5.2 Latchup Triggering
For latchup to occur the parasitic npn-pnp circuit has to be triggered and
the holding state has to be maintained. Latchup can be triggered by
transient cur-rents or voltages that may occur internally to a chip during
power-up or externally due to voltages or currents beyond normal
operating ranges. Radiation pulses can also cause latchup. Two distinct
methods of triggering are possible, lateral triggering and vertical
triggering.
Lateral triggering occurs when a current flows in the emitter of the lateral
npn-transistor. The static trigger point is set by

I ntrigger ~ V pnp-on (1.1)
α npn R well
where

V pnp _ on~ 0.7 volts the turn-on voltage of the vertical pnp-transistor

anpn = common base gain of the lateral npn-transistor

Rwell = well resistance.
Vertical triggering occurs when a sufficient current is injected into the
emitter of the vertical-pnp transistor. Similar to the lateral case, this
current is multiplied by the common-base-current gain, which causes a
voltage drop across the emitter base junction of the npn transistor due to
the resistance, R substrate . When the holding or sustaining point is entered, it
represents a stable operating point provided the current required to stay in
the state can he maintained.
Current has to be injected into either the npn- or pnp-emitter to initiate
latchup. During normal circuit in internal circuitry this may occur due to
supply voltage transients, but this is unlikely. However, these conditions
may occur at the I/O circuits employed on a CMOS chip, where the
internal circuit voltages meet the external world and large currents can
flow. Therefore extra precautions need to be taken with peripheral CMOS
circuits.



a

b

Figure 1.25 Externally included latchup
Figure 1.25(a) illustrates an example where the source of an nMOS output
transistor experiences undershoot with respect to Vss due to some external
circuitry. When the output dips below Vss by more than 0.7V, the drain of
the nMOS output driver is forward biased, which initiates latchup. The
complementary case is shown in figure 1.25(b) where the pMOS output
transistor experiences an overshoot more than 0.7V beyond VDD . Whether
or not in these cases latchup occurs depends on the pulse widths and
speed of the parasitic transistors.
1.4.6 Latchup Prevention
For latchup to occur an analysis of the circuit in figure 1.25(b) finds the
following inequality has to be true

βnpnβpnp> 1+ (βnpn+1 ) I Rsubstrate +I Rwellβpnp) (1.2)
I
DD - I Rsubstrate

Where
I
Rsubstrate == Vbe npn
R
substrate
I
Rwell = Vbe pnp
Rwell
IDD =total supply current


This equation yields the keys to reducing latchup to the point where it
should never occur under normal circuit conditions. Thus, reducing the
resistor values and reducing the gain of the parasitic transistors are the
basis for eliminating latchup.
Latchup may be prevented in two basic ways:
• Latchup resistant CMOS processes.
• Layout techniques.

A popular process option that reduces the gain of the parasitic transistors
is the use of silicon starting-material with a thin epitaxial layer on top of a
highly doped substrate. This decreases the value of the substrate resistor
and also provides a sink for collector current of the vertical pnp-transistor.
As the epi layer is thinned, the latchup performance improves until a point
where the up-diffusion of the substrate and the down-diffusion of any
diffusions in subsequent high-temperature procession steps thwart
required device doping profiles. The so-called retrograde well structure is
also used. This well has a highly doped area at the bottom of the well,
whereas the top of the well is more lightly doped. This preserves good
characteristics for the pMOS (or nMOS in p-well) transistors but reduces
the well resistance deep in the well. A technique linked to these two
approaches is to increase the holding voltage above the VDD supply. This
guarantees that latchup will not occur.
It is hard to reduce the betas of the bipolar transistors to meet the condi-
tion set above. Nominally, for a 1µ n-well process, the vertical pnp has a
beta of 10-100, depending on the technology. The lateral npn-current-
gain which is a function of n+ drain to n-well spacing , i s b e t w e e n 2
and 5.
1.5 LAYOUT DESIGN RULES
Layout rules, also referred to as design rules, can be considered as a pre-
scription for preparing the photomasks used in the fabrication of
integrated circuits. The rules provide a necessary communication link
between circuit designer and process engineer during the manufacturing
phase. The main objective associated with layout rules is to obtain a
circuit with optimum yield (functional circuits versus nonfunctional
circuits) in as small an area as possible without compromising reliability
of the circuit.
In general, design rules represent the best possible compromise between
performance and yield. The more conservative the rules are, the more
likely it is that the circuit will function. However, the more aggressive the

rules are, the greater the probability of improvements in circuit
performance. This improvement may be at the expense of yield.
Design rules specify to the designer certain geometric constraints on the
layout artwork so that the patterns on the processed wafer will preserve
the topology and geometry of the designs. It is important to note that
design rules do not represent some hard boundary between correct and
incorrect fabrication. Rather, they represent a tolerance that ensures very
high probability of correct fabrication and subsequent operation. For
example, one may find that a layout that violates design rules may still
function correctly, and vice versa. Nevertheless, any significant or
frequent departure (design-rule waiver) from design rules will seriously
prejudice the success of a design.
Two sets of design-rule constraints in a process relate to line widths and
interlayer registration. If the line widths are made too small, it is possible
for the line to become discontinuous, thus leading to an open circuit wire.
On the other hand, if the wires are placed too close to one another, it is
possible for them to merge together; that is, shorts can occur between two
independent circuit nets. Furthermore, the spacing between two
independent layers may be affected by the vertical topology of a process.
The design rules primarily address two issues:
(1) The geometrical reproduction of features that can be reproduced by
the mask- making and litho-graphical process and
(2) The interactions between different layers.
There are several approaches that can be taken in describing the design
rules. These include 'micron' rules stated at some micron resolution, and
lambda (λ) based rules. Micron designs rules are usually given as a list
of minimum feature sizes and spacings for all masks required in a given
process.
1.5.1 Layer Representations
The advances in the CMOS processes are generally complex and
somewhat inhibit the visualization of all the mask levels that are used in
the actual fabrication process. Nevertheless the design process can be
abstracted to a manageable number of conceptual layout levels that
represent the physical features observed in the final silicon wafer. At a
sufficiently high conceptual level all CMOS processes use the following
features:
• Two different substrates.
• Doped regions of both p- and n-transistor-forming material.
• Transistor gate electrodes.

• Interconnection paths.
• Interlayer contacts.

The layers for typical CMOS processes are represented in various figures
in terms of:
• A color scheme proposed by JPL based on the Mead-Conway colors.
• Other color schemes designed to differentiate CMOS structures
(e.g., the colors as used on the from cover of this hook)
• Varying stipple patterns.
• Varying line styles.
Some of these representations are shown in below table.

1.5.2 CMOS n-well Rules
In this section a version of n-well rules based on the MOSIS CMOS
Scalable Rules and compares those with the rules for a hypothetical
commercial 1µ CMOS process shown in below table. The MOSIC rules
are expressed in terms of λ. These rules allow some degree of scaling
between processes as, in principal, we only need to reduce the value of λ and
the designs will be valid in the next process down in size. Unfortunately, history
has shown that processes rarely shrink uniformly. Thus industry usually uses the
actual micron-design rules and codes designs in terms of these dimensions, or
uses symbolic layout systems to target the design rules exactly. At this time, the
amount of polygon pushing is usually constrained to a number of frequently used

standard cells or memories, where the effort expended is amortized over many
designs. Alternatively, the designs are done symbolically, thus relieving the
designer of having to deal directly with the actual design rules.
The rules are defined in terms of:
• Feature sizes.
• Separations and overlaps.



1.5.3 Scribe Line
The scribe line is specifically designed structure that surrounds the
completed chip and is the point at which the chip is cut with a diamond
saw. The construction of the scribe line varies from manufacturer to
manufactures
1.5.4 SOI Rules
SOI rules closely follow bulk CMOS rules except the n+ and p+ regions
can abut. This allows some interesting and latch circuits. A spacing rule
between the poly and island edges. This can be caused by thin or faculty
oxide covering over the islands.


1.5.5 Layer Assignments
The below table lists the MOSIS Scalable CMOS design-rule layer
assignments for the Caltech Intermediate Form (CIF) and Calma stream
format.

1.6. PHYSICAL DEISGN
1.6.1 Basic Concept
Figure 1.26 shows part of the design flow, the physical design steps, for
an ASIC (omitting simulation, test, and other logical design steps that
have already been covered). Some of the steps in Figure 1.26 might be
performed in a different order from that shown. For example, depending
on the size of the system, perform system partitioning before any design
entry or synthesis. There may be some iteration between the different
steps too. First to apply system partitioning to divide a microelectronics
system into separate ASICs.
In floorplanning sizes estimate and set the initial relative locations of the
various blocks in our ASIC (sometimes we also call this chip planning).

At the same time to allocate space for clock and power w i r i n g a n d
decide on the location of the I/O and power pads. Placement defines the
location of the logic cells within the flexible blocks and sets aside space for
the interconnect to each logic cell. Placement for a gate-array or standard-
cell design assigns each logic cell to a position in a row.

Figure 1.26 Part of ASIC Design Flow
For an FPGA, placement chooses which o f the fixed logic resources on the
chip are used for which logic cells. Floorplanning and placement are
closely related and are sometimes combined in a single CAD tool.
Routing makes the connections between logic cells. Routing is a hard
problem by itself is normally split into two distinct steps, called global
and local routing. Global routing determines where the interconnections
between the placed logic cells and blocks will be situated. Only the routes
to he used by the interconnections within the wiring areas.
Global routing is sometimes called loose routing for this reason. Local
routing joins the logic cells with interconnections. Information on which
interconnections areas to use comes from the global router. Only at this
stage o f layout d, finally decide on the width, mask layer, and exact
location of the interconnections local routing is also known as detailed
routing.



1.6.2 CAD Tools sets
In order to develop a CAD tool it is necessary to convert each of the
physical do steps to a problem with well-defined goals and objectives. The
goals for each physical design step are the things to achieve. The
objectives for each step things to meet goals. Some examples of goals and
objectives for each of the ASIC physical design steps are as explained
below,
System partitioning
• Goal: Partition a system into a number of ASICs.
• Objectives: Minimize the number of external connections between the
ASICs. Keep each ASIC smaller than a maximum size.
Floorplanning
• Goal: Calculate the sizes of all the blocks and assign them locations.
• Objective: Keep the highly connected blocks physically close to each
other.
Placement
• Goal: Assign the interconnect areas and the location of all the logic
cells within the flexible blocks.
• Objectives: Minimize the ASIC area and the interconnect density.

Global routing
• Goal: Determine the location of all the interconnect.
• Objective: Minimize the total interconnect area used.
Detailed routing
• Goal: Completely route all the interconnect on the chip.
• Objective: Minimize the total interconnect length used.

There i s no magic recipe involved in the choice o f the ASIC physical
design steps. These steps have been chosen simply because, as tools and
techniques have developed historically, these steps proved to be the
easiest way to split up the larger problem if ASIC physical design.


1.6.3 Physical Design-The Inverter

1.6.4 Physical Design-The NOR



1.6.5 Physical Design-The NAND

1.7 DESIGN STRATEGIES
The economic viability of an IC is in large part affected by the productivity
that can be brought to hear on the design. This in turn depends on the
efficiency with which the design may be converted from concept to
architecture, to logic and memory, to circuit and hence to a physical layout.
A good VLSI design system should provide for consistent in all three
description domains (behavioral, structural and physical) and at all relevant
levels of abstraction (architecture, RTL, logic, circuit). The means by which
this is accomplished may be measured in various terms that differ in
importance based on the application. These design parameters may be
summarized in terms of
• Performance-speed, power, function, flexibility.
• Size of die (hence cost of die).
• Time to design (hence cost of engineering and schedule).
• Ease of test generation and testability (hence cost of engineering and
schedule).
Design is a continuous trade-off to achieve adequate results for all of the
above parameters. As such, the tools and methodologies used for a
particular chip will be a function of these parameters. Certain end results
have to be met (i.e., the chip must conform to performance specifications),
but other constraints may be a function of economics (i.e., size of die
affecting yield) or even subjectivity (i.e., what one designer finds easy,
another might find incomprehensible).


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