Fully_balanced_transimpedance_amplifier_

1. Analog IC Design (ENE521000) Hsin Chen
Homework #4
Due date : 12th Dec 2005
(1) Design of a two-stage operational amplifier
Consider the two-stage operational amplifier in Fig.1. VDD=3V, Vss=0V, and
CL=10pF. Please design IBias and the sizes of all transistors to satisfy the following
specifications
Specifications Units
DC characteristics Pdiss ≦ 1.5 mW
1≦ ICMR ≦ 2.5 V
0.5≦ Vout range ≦ 2.5 V
AC characteristics AV ≧ 5000 V/V
GB ≧ 5M Hz
PM ≧ 60 °
Transient characteristic Slew rate ≧ 10 V/µs
Fig.1
(a) Design Ibias , Cc and W/L of all transistors by hand calculation.
(Let λN = 0.01, λP = 0.03, and estimate other Level 1 parameters as before)
(b) Use Spice to check whether all specifications are satisfied. If not, redesign
your circuit to meet the specifications. The following results must be
included in your report.
(i)Connect the Op-amp you designed as the configuration in Fig.6.6-10 in the

2. textbook. Plot vout and ID(M5) v.s. vin. Mark explicitly the input-common mode
range in the plot.
(ii) Connect the Op-amp as the configuration in Fig.6.6-11. Plot vout v.s. vin. Mark
explicitly the Vout range in the plot.
(iii) Plot the open-loop frequency response (both magnitude and phase) of the
Op-amp. Mark explicitly AV, GB, and PM in the plot.
(iv) Connect the Op-amp as the configuration in Fig.6.6-14, and send the signal
in Fig.2 to vin+. Plot vin and vout v.s. time. From this result, calculate the positive
and negative slew rates of the Op-amp.
(v) Plot the frequency response of the PSRR+ of the Op-amp
Fig.2
(c) Summarise the specifications of the Op-amp in a table of the following form
for five corners (TT, SF, FS, SS, FF).
Specifications Simulations Units
DC Pdiss ≦ 1.5 mW
characteristics 1≦ ICMR ≦ 2.5 V
0.5≦ Vout range ≦ 2.5 V
AC AV ≧ 5000 V/V
characteristics GB ≧ 5M Hz
PM ≧ 60 °
Transient Slew rate ≧ 10 V/µs
characteristic
PSRR+ (100Hz) N/A dB
PSRR+ (10kHz) N/A dB
(d)Please submit your netlist file (*.netlist) to the FTP site
ftp: 140.114.23.229
login: aic password: aic
Upload your *.netlist and *.gds into the HW4 folder before the Deadline
Note that your design will be an Hspice subcircuit that we will include in our

3. test circuits. Therefore, your netlist should provide everything in the Op-amp as
shown in Fig.3 and use EXACTLY the SAME node names in Fig.3.
Your subcircuit syntax will be as follows:
.subckt opamp <pi> <ni> <o> <vdd> <gnd>
*Your amp goes here
.ends opamp
Fig.3