Cs cmos a low-noise logic family for mixed signal

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
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ISSN 0976 – 6472(Online)
Volume 4, Issue 2, March – April, 2013, pp. 180-190
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CS-CMOS: A LOW-NOISE LOGIC FAMILY FOR MIXED SIGNAL
SOCS

Aswathy G Nair1, Gopakumar M G2
1
Student,M.Tech(VLSI& Embedded Systems), Mangalam,Ettumanoor,India
2
Asst. Professor, Deptt. Of ECE, Mangalam, Ettumanoor, India

ABSTRACT

Managing the switching-noise in mixed-signal systems fabricated on a single chip is
becoming increasingly challenging. Existing logic families that minimize switching-noise
generation, Such as current-steering logic (CSL), current-balanced logic (CBL) etc. require
considerably more power than traditional CMOS implementations. We present a new logic
family called the current-steering CMOS (CS-CMOS) obtained by a simple modification
keeping the core CMOS structure in tact to preserve its most attractive features. This family
not only reduces the switching noise by a factor of ten but also delivers five times higher
speed than CSL and CBL for the same power consumption. A comparison with existing
alternative circuits shows that, for the same supply voltage and the same power consumption,
the new circuits have smaller area and lower delay.

Keywords: Current-balanced logic (CBL), Current-steering CMOS (CS-CMOS), current
steering logic, Mixed signal system-on-chip (SoC), Power supply noise.

1. INTRODUCTION

VLSI systems-on-chip (SoCs) use CMOS digital-logic circuits because they consume
very low power, have high packing density and are easy to design. Most of the power
consumed by CMOS gates is due to displacement currents drawn during state-transitions for
charging and discharging wire and device capacitances. These increase linearly with the
operating frequency and flow through the power supply wires, ground lines, parasitic
inductances and capacitances causing ringing and voltage drop. This is the dominant source
of substrate noise. Injection of this noise into sensitive analog circuits can cause serious
impairments in their performance. Typical examples are increased jitter in voltage-controlled
oscillators and reduction in the dynamic range of analog-to-digital converters, etc.

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In mixed signal integrated circuits, there is a digital sector that generates switching
noise and an analog sector to which the noise is coupled via the substrate, which is shared by
the two sectors. The noise coupling can be reduced, to some extent, by careful layout and
routing. Further noise reduction is necessary, and this is the purpose of new low-noise logic
families, that are expected to generate less noise into the substrate than conventional CMOS
digital circuits. The most interesting of the new families, due to their simpler structure, are
current-steering logic (CSL) and current-balanced logic (CBL). Reduced noise in CSL and
CBL circuits is obtained by having an ideally constant supply current. Due to non-ideal
effects, the supply current still has spikes associated with the output voltage transitions, but
their amplitude is reduced by one to two orders of magnitude with respect to CMOS.
However, the substrate noise depends on the time derivative of the supply current, and not on
the amplitude of its variations; furthermore, there are other sources of substrate noise, in
addition to the supply current. Variation. Thus, to evaluate the effective improvement
obtained with CSL or CBL it is necessary to consider the actual substrate noise.

2. SUBSTRATE NOISE IN MIXED-SIGNAL CIRCUITS

In mixed-signal integrated circuits, the digital sector and the analog sector share a
common substrate. In Fig. 1 we represent one transistor of the digital sector and one transistor
of the analog sector. In a lumped element equivalent circuit the substrate is modeled by a
single “substrate node” connected to the other nodes in the digital and analog sectors by
parasitic resistances and capacitances, some of which are shown in Fig. 1 (the resistances
shown would ideally be short circuits, and the capacitances would be open circuits).

This single-node approach was originally adopted for dual layer
substrates (thin lightly doped, high resistivity epitaxial layer grown on top of a thick, heavily
doped, low resistivity bulk layer) used in digital technologies. It has been shown that this
approach is also applicable to single-layer homogeneous substrates. In and the results
obtained assuming a single-node substrate representation, for both low-resistivity and high-
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resistivity substrates, do not differ substantially from the results obtained using a more
conventional simulation procedure (boundary element method). In dual-layer substrates, the
substrate node corresponds physically to the heavily doped bulk layer, which behaves as a
single node. In single-layer substrates, the substrate node has meaning only for modeling
purposes. One of the terminals of the external voltage supply is the “ground,” i.e., the
common reference to all signals, digital and analog. The connection to the supply voltage has
inductance and resistance, but only the inductance is included in Fig. 1, since the effect of the
resistance can be neglected. The substrate noise is the voltage between the substrate node and
the ground terminal. The substrate noise originated by the switching of the digital cells has
two main sources, which are referred to here as supply noise and capacitive noise.
Supply noise—The supply current spikes that occur during the state transition of the digital
cells are translated into a voltage, L dIDD/dt which influences the substrate node voltage.
This increases with the supply inductance and with the steepness of the current spikes.
Capacitive noise—the voltage steps at the nodes of the digital cells are coupled to the
substrate node through the parasitic capacitances.
An additional source of substrate noise is impact ionization, which may be
significant in advanced technologies with a very thin oxide under the gate. The substrate
noise voltage affects the analog cells due to the body effect and due to the capacitive coupling
to the transistor terminals. This effect increases with the coupling areas (capacitances) and the
steepness of the voltage variation. The supply noise can reach hundreds of mill volts, and has
been regarded as a major cause of performance degradation in mixed-signal circuits.

3. LOW-NOISE LOGIC FAMILIES

The common principle of the low-noise logic families that have been proposed for use
in mixed-signal circuits is to have a supply current that is ideally constant. Due to non-ideal
effects, it still has switching spikes, but their amplitude is strongly reduced, with respect to
CMOS digital circuits. In the first families that were proposed the constant supply current is
obtained by having the connection to the power supply through a current source. These low-
noise families include source-coupled logic folded source-coupled logic nMOS CBL, and
CSL. Some of these families have limited practical interest, due to their complicated
structure, with a large number of devices and terminals, which leads to large area and power
dissipation and also to difficult routing.

4. PREVIOUS WORKS: CURRENT-STEERING LOGIC (CSL) & CURRENT
BALANCED LOGIC (CBL)

Current-steering logic (CSL) and current-balanced logic (CBL) are logic
families that have been proposed with the objective of reducing the substrate noise in mixed-
signal integrated circuits

4.1 CSL (current-steering logic)

The most interesting of these families is CSL, since CSL circuits are much simpler.
The structure of a CSL gate is shown in Fig. 2(a), where the nMOS logic block is the same
that would be used between the output and ground in an nMOS gate or in a CMOS gate. The
supply current IDD is steered to ground through the nMOS block when this is in the low
resistance state (output low); otherwise it is sank through the diode connected transistor M3

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(output high). The special case of the CSL inverter is shown in Fig. 2(b), where the nMOS
block is reduced to transistor M1, and the current source is realized by transistor M2 with a
constant bias voltage VB.

These limitations can be overcome by using a different principle to obtain a constant
supply current, a current equalizer transistor is used instead of a current source, thus leading
to a different family, CBL.

4.2 CBL (current balanced logic)

In mixed-signal (i.e., analog–digital) integrated circuits, the noise generated in the
digital section affects the performance of the analog section. An important source of noise is
the supply current spikes during logic transitions. To avoid these, the current-steering logic
(CSL) family has been proposed. By using a current source, the supply current IDD is ideally
constant. In practice, supply current spikes still exist, but their amplitude is reduced by up to
two orders of magnitude with respect to conventional CMOS logic circuits. In this paper we
propose the new current balanced logic family (CBL), which has advantages with respect to
the existing CSL family.
The new circuits achieve ideally constant supply current by using a different
principle. They may be regarded as pseudo- NMOS circuits to which transistor M3 has been
added. The objective is that, during logic transitions, the variation of iD3 compensates (or
balances and, hence, the designation current balanced Logic) the variation of iD2

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We find that perfect compensation can be obtained, thus making iD3 + iD2 =
IDD constant, if transistors M2 and M3 are matched
Vtn = Vtp = Vt
K3 = K2 = K
where Vtn and Vtp are the threshold voltages of the NMOS and PMOS transistors,
respectively,

with the usual meaning for µ (mobility), Cox (gate oxide capacitance), and W/L (aspect
ratio).

5. POPOSED WORKS: CURRENT STEERING CMOS (CS-CMOS)

The problem of switching noise is dealt in three parts: noise generation, its
propagation through the substrate, and injection in to analog circuits. The focus here is to
minimize the generation of switching noise and keeping the impulse current local to where it
is generated. Among the existing logic families that use this approach are current steering
logic (CSL) and current balanced logic (CBL). Both of these families reduce noise because
they draw a constant-current from the supply. But the power consumption is higher than that
of the equivalent CMOS implementation.

5.1 CS-CMOS LOGIC

5.1.1 Static Transfer Characteristics

CS-CMOS is obtained by a simple current-steering modification to the standard
CMOS family. As in a CMOS inverter, a pair of complimentary transistors (M1-M2)
connected in series forms the core of the proposed CS-CMOS inverter, as shown in Fig.5.
Since CMOS gates do not draw any appreciable current in their static states, constant-current

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operation requires additional paths for the d-c bias current to flow. A pair of complimentary
transistors(M3,M4) is added in parallel for this purpose. A P-channel transistor M5 sources a
constant-current IB to each gate.
When is VIN HIGH M1 is OFF and M2 is ON. The output node voltage VOUT
is LOW turning M3 ON and IB flows in M3. Note that minimum output LOW
voltage(VOL) for CS-CMOS is same as in CMOS. This is not so for the other single-ended
ratioed logic families such as CSL and CBL. When is VIN low the output node is HIGH,M4
conducts and IB is steered into it. Assuming the square-law model for the transistors,
maximum output voltage

(VOH) can be computed as

…….(1)

Figure 5. CS-CMOS inverter

In the above equation µ represents the carrier mobility, COX is the oxide
capacitance per unit-area, W represents the width and , the L length of the transistor. To have
an appreciable overdrive voltage (VDSAT) for a given current, minimum-width devices are
chosen for M3 and M4 Such a choice causes minimal loading and hence does not appreciably
affect the speed of the inverter.
The node X with the capacitor in Fig. 5.acts like a local power supply for the CMOS
inverter M1-M2. If VX>VT1+VT2 , the inverter (M1-M2) operates like a regular CMOS
circuit in which there is an input voltage range for which both M1 and M2 will conduct
simultaneously. When this happens a part of IB flows through this path between the node X
and ground. For VX<VT1+VT2 , as VIN increases from LOW to HIGH,M1 will shut OFF
before M2 turns ON and for decreasing VIN, M2 will shut OFF before turns M1 ON. The
ideal choice is to make VX= VT1+VT2. If the threshold voltages of are chosen to be equal to
those of M3-M4 , this criterion cannot be met. This is because the magnitude of VX is the
gate-source voltage of M3 or M4 given by (1). But if the threshold voltages of M1-M2 are
chosen to be smaller than those of M3-M4 a reduction in hysteresis can be achieved. Thus
the threshold voltages for M1 and M2 are chosen such that VT1+VT2=VT4+VDSAT4.

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DC transfer-characteristics of the inverter shownFig.6..Consider the output pull-up
transition. Initially, when VIN is HIGH, VOT is LOW and M3 carries the bias current IB .
As VIN decreases M1 starts conducting. Now M1-M3 forms a current-biased p-channel
differential- pair with M2 acting as an active- load. Let the incremental d-c trans conductance
of the pair gmd be and the output-conductance due to M1 and M2 in parallel, .

Routine small-signal Analysis ,gives

Here the lower-case symbols represent incremental quantities.
Equation (2) indicates the presence of positive feedback in the CS-CMOS inverter.
When we consider M2 as an active load of the differential pair, it is easy to identify the
circuit as a Schmidt-trigger containing positive feedback via the output of the inverter and the
node X . Initially as VIN is HIGH, gmd is small as M1 is OFF. Furthermore g0 is large since
M2 operates in its triode region. Hence the incremental gain A is <<1. As VIN decreases, M1
begins to conduct and decreases causing the gain to increase. A>=1 leads to regeneration and
switching. Thus the presence of positive feedback causes high gain during the transitions (see
Fig. 6). Such a high gain does not happen in the other logic families having no feedback.

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5.1.2 Dynamic Characteristics

The speed of low noise logic families is limited by the bias current IB. In CS-CMOS
the additional capacitor CD added at the node X (see Fig. 6) acts as a decoupling capacitor.It
supplies most of the charge required to pull up the load-capacitance. Although the current
supplied from the power supply is fixed, the capacitor CD makes it operate virtually like
irregular CMOS circuit. The size of the CD for CS-CMOS gates is chosen as follows. For an
allowable change at the power supply node (vx) during the pull-up transition, the value
of
required can be estimated as

…….(3)

where is the load CL capacitance consisting of the wire and device capacitances
at the output node. Restricting the number of fan-outs of a gate can keep the size of CD
sufficiently large and yet keep the size of the CS-CMOS gate manageable. For both CSL and
CBL gates the pull-up rise-time and delay are controlled by the bias current, but the voltage
across the capacitor CD in CS-CMOS provides a quadratic current similar to that in standard
CMOS.
A key reason for the widespread use of digital CMOS is its, very low power
consumption. However, low noise implementations like CSL and CBL consume an order of
magnitude higher power . CS-CMOS attempts to bridge this gap by using the capacitor CD
which provides most of the charge during the pull-up operation. This boosts the performance
of CS-CMOS substantially. The charge lost by CD during the pull-up is replenished by the
bias current . The required bias current can thus be estimated as

...................(4)

For CSL and CS-CMOS inverters the bias current is adjusted by changing the
voltage VBIAS . For CBL inverters the current is adjusted by varying the supply voltage. It
can be observed that the CS-CMOS inverters can achieve less than 1 ns delay for bias
currents greater than 1 A.

5.2 Current Supply Spikes

Displacement current pulses flowing through the inductances of ground wires causes
noise spikes known as ground bounce. Noise is also injected into the substrate from the
source and drain nodes of the MOS devices during transitions. This is known as capacitive
noise coupling to the substrate. Yet another noise source is due to impact ionization. CSL,
CBL and
CS-CMOS gates have minimal displacement currents in the power-supply line
because of the constant-current operation. Thus capacitive coupling into the power
supply/substrate is the dominant source of noise injection for these logic families .The
parasitic capacitances associated with the CS-CMOS inverter are shown in Fig. 7. These are

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the CCS (the drain-well capacitance of the PMOS transistor M5) and the capacitor CD. When
a step input is applied to the inverter a displacement current I is supplied from the node X to
pull up the output node X. A fraction of this current Isup is supplied from power supply
through the parasitic capacitance CCS but most of it is delivered by CD.

Fig. 7. Parasitic capacitances in a CS-CMOS inverter used to estimate the fraction
of current flowing into the power supply.

This fraction is estimated as

......(5)

This fraction can be reduced either by increasing the value CD of or by decreasing
the value of CCS. The value of CD is chosen based on the load capacitance. CCS depends
on the size of the transistor M5.

6. COMPARISON OF CBL, CSL WITH CS-CMOS

TABLE:1

INVERTER NO OF POWER DELAY(ns) PDP(10^-12 EDP(10^-
TRANSISTORS W-S) 21 W-S^2)
CBL 3 0.263mw 0.860 0.22618 0.1945
CSL 3 0.117mw 1.69 0.1973 0.334163
CS-CMOS 5 53.039µw 0.48 0.025584 0.0122823

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7. EXPERIMENTAL RESULTS

The noise reduction provided by low-noise logic cells has been assessed simply by
considering the amplitude of the supply current variation. This, however, is very insufficient,
since it ignores capacitive noise, and it is not even a rigorous indicator of supply noise, which
depends on LdIDD/dt. What really matters is the substrate voltage (Fig. 1), and this will be
used here to compare the noise performance of CSL, CBL, and conventional CMOS.
In this section the inverters are designed using CBL,CSL,and CS-CMOS, existing
logic families like CSL ,CBL and new logic family like CS-CMOS compared in terms power
consumption ,delay and noise.The 0.18µm technology parameters provided by predictive
technology are used at 1.8V. The decoupling capacitor CD is the value 0.01pF are used,
resulting average power consumption is observed.
Calculating energy delay product based on the measured propagation delay (see
TABLE:1) show that the CS-CMOS consumes much lower power than the CSL especially at
lower bias currents. Using larger would improve energy-delay product as well.
CS-CMOS and CSL families utilize a fixed IB variation in supply do not affect their
performance as much as in CMOS implementations. The supply current varies with channel
length modulation of the current source device. As the propagation delay is linearly
dependent on bias current for both the families, a small variation was observed in
measurements as well. Using larger channel length devices for the Current sources would
reduce this variation but will need higher voltage headroom

7. CONCLUSION

We present a new low-noise logic family called CS-CMOS for noise reduction in
mixed-signal integrated-systems containing both DSP as well as sensitive analog circuits
such as phase-lock loops and data converters in a single chip of silicon. The new family is
obtained by a simple current-steering modification to the standard CMOS logic preserving
most of the attractive features of CMOS. The well-known constant-current enables a
substantial reduction of switching noise. Extensive simulations and measurements
demonstrate the speed and power advantages of this family over previously proposed logic
families namely CSL and CBL.

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