1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
INTERNATIONAL JOURNAL OF ELECTRONICS AND
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 4, Issue 6, November - December, 2013, pp. 85-92
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IJECET
©IAEME
VLSI IMPLEMENTATION OF HUFFMAN DECODER USING BINARY
TREE ALGORITHM
VIJAYAKUMAR SUVVARI1, M.V.H. BHASKARA MURTHY2
1
2
(M-Tech Student, Department of ECE, AITAM College,
Tekkali, Srikakulam Andhra Pradesh, India)
(Associate Professor, Department of ECE, AITAM College,
Tekkali, Srikakulam Andhra Pradesh, India)
ABSTRACT
Compression is useful technique in digital system, as it reduces the channel bandwidths and
storage size. This paper presents Huffman decoder based on new binary tree method for improving
usage of memory and Bandwidth.
The proposed Huffman decoder is implemented by using ASIC and FPGA design
methodologies. To implement the encoder and decoder architectures, 0.6 Micron standard cell library
was used for ASIC implementation. Various performance metrics like leakage power, dynamic
power, area and number of registers are obtained by using ASIC and FPGA implementations and the
results are compared. The simulations are carried out by using Modelsim tool.
Keywords: ASIC, Binary tree, Data compression, Decoding algorithm, FPGA.
1. INTRODUCTION
The Huffman code is one of the Variable Length Codes (VLC) which compresses the data
size. The advantages of this compression algorithm are efficient utilization of channel bandwidth and
storage size. Therefore, Audio and Video standard organizations research on the Huffman code to
apply another improved method like MP3 and H.264. Also the Huffman code is adopted in the data
compression for a long time. Following section explains about the significance of the project and
implementations.
The major disadvantage of array Data Structure is the memory cost spent on storing such a
complete binary tree by using an array, which also results in a slow decoding speed. In order to solve
the problem, we can use a New Binary tree Algorithm method [1]. The advantage of this method for
representing the Huffman decoder is that original data is retrieved easily and requires less memory.
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2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
2. THE PROPOSED METHOD
2.1 The Proposed Huffman Decoder
The proposed Huffman decoder will be implemented on ASIC. The advantage of the
algorithm will be proved by extensive simulations and from prototyping. The performance will be
measured in terms of power dissipation. For power and area calculations, FPGA tools and ASIC
development tool will be used [2]. The customized Huffman hardware decoder’s performance will be
compared with different platforms.
2.2 Description of Huffman Coding
Given a set of symbols and their weights (usually proportional to probabilities), Find a prefixfree binary code (a set of code words) with minimum expected codeword length (equivalently, a tree
with minimum weighted path length from the root) [4].
Formalized description:
Input:
Alphabet, A={a1, a2, a3,…..} which is the symbol of the alphabet of size-n .Set , W={w1,w2,…}
which is the set of the (positive) symbol weights (usually proportional to probabilities)
i.e. w1= weight (ai), 1≥i≥n.
Output.
Code C=(A,W), C= {c1, c2….} Which is the set of (binary) codeword’s, where ci is the codeword
for ai, 1≤i≤n.
Goal:
n
L(C) =
∑ w L(c ) × length (Ci)
i
i
(1)
i =1
Let (1) be the weighted path length of code C.
Condition: L(C) ≤ L(T) for any code T(A,W).
For any code that is biunique, meaning that the code is uniquely decodable, the sum of the
probability budgets across all symbols is always less than or equal to one. In this example, the sum is
strictly equal to one as a result, the code is termed a complete code. If this is not the case, you can
always derive an equivalent code by adding extra symbols (with associated null probabilities), to
make the code complete while keeping it biunique.
As defined by Shannon, the information content h (in bits) of each symbol ai with non-null
probability is:
h ( i ) = log 2 (
1
)
wi
(2)
The entropy H (in bits) is the weighted sum, across all symbols ai with non-zero probability wi, of the
information content of each symbol:
1
) = − ∑ wi log 2 wi
(3)
wi
wi > 0
wi > 0
wi > 0
(Note: A symbol with zero probability has zero contribution to the entropy, since
=0. So for simplicity, symbols with zero probability can be left out of the formula
H ( A) =
∑ w h(a ) = ∑ w
i
i
above.)
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3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
2.3 Encoder and Decoder for Text
The Huffman decoder is implemented for text. The text compression involves its encoding,
the text decoder contains the Huffman decoder for obtaining the original text. The Huffman tree used
by encoder and decoder is shown Fig 2.1 [3]. The alphabet consists of the uppercase letters and the
space. All left branches are labeled 0, and all right branches are labeled 1.
This tree is based on the following assumed frequencies. E 130 T 93 N 78 R 77 I 74 O 74
A 73 S 63 D 44 H 35 L 35 C 30 F 28 P 27 U 27 M 25 Y 19 G 16 W 16 V 13 B 9 X 5 K
3 Q 3 J 2 Z 1
Figure 2.1 binary trees for Text
It is assumed that there are 130 Es and 182 spaces for every 1000 letters. The encoder
retrieves the code for each symbol from a map, and shifts it out one bit at the time. The decoder is a
finite state machine whose state transition graph is obtained from the tree by adding acs(add compare
select) from the leaves back to the top of the tree [6]. Each node uses ten bits for its encoding. The
code of the root is 0. If a state is not a leaf of the tree, and its encoding is n, then the encodings of its
two children are 2n+1 and 2n+2.
2.4 The Hardware Implementation of Algorithm
Encoder:
Figure 2.2 Block diagram of Encoder
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4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
The fig 2.2 shows the block diagram of Encoder and Code for each character which comes
from the tree shown in Fig 2.1 is stored in LUT (LOOK UP TABLE). Character input which is given
to the encoder acts as input to the LUT which gives corresponding encoded word on the data bus
which is given to a shift register so as to serially shift the data out. As it is a variable length coding,
in order to determine the end of the code word for each character while shifting out, one more bit is
added to the end of the code word in the LUT is made as 1. The code word is logically shifted out till
it contains only 1 at its LSB. Then next character is loaded from the ROM. Apart from this, the
encoder should generate an enable signal to the decoder so that the decoder knows when the valid
data is presented to it.
Decoder:
Both encoding and decoding should be done with respect to the same tree. So, same data
which is stored in the encoder LUT is stored in the decoder LUT in a different way. The Fig.2.3
below shows the block diagram of Huffman Decoder and clearly explains the operation.
Fig 2.3 Block diagram of Huffman Decoder
There will be a LUT which consists of the mapping from encoded data stream to the regular
characters. Initial state starts with 0. Based on state value some character comes out of LUT which
will be either 0 or valid character. Comparator output will be either 0 or 1 depending on the contents.
If it is 0, the state will be left shifted and given as input to adder if not 0 will be fed to the adder
meaning that an encoded value is decoded. Depending on the serial cipher input either 1 or 2 is given
as input to adder. Both the inputs are added and registered to get the state which is fed to the LUT.
This process is continuous for the serial cipher input.
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5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
3. SIMULATION AND RESULTS
3.1 ASIC & FPGA Implementation
Figure 3.1 Implementation Flow using Xilinx13.1 ISE tool
Figure 3.1 shows the flow that is followed in implementing a design on Xilinx FPGA using
the tool Xilinx13.1 ISE.
3.2 Power & Area Analysis
The leakage power (static) and dynamic power analysis of the design can be done by using
Xilinx13.1 Power Analyzer. To analyze the dynamic power, the design file imported from Place and
Route (i.e., “.ncd file”) and physical constraint file (i.e., “.pcf file”) are required. Along with these
files, a value change dump (“.vcd”) file is required [5]. Hence to estimate the switching power, the
design has to be synthesized to target FPGA. Now, by using the XPower Analyzer, the three files ,
.ncd file, .pcf file and .vcd file, are included to determine , static and dynamic power consumption of
the design.
Performance Metric
Leakage power
Dynamic Power
Area
Total no of registers
Table 3.1. Power and Area Analysis Report
ASIC Implementation (0.6Micron
FPGA Implementation
CMOS Digital library)
(Xilinx Spartan 2s)
33.25 nW
1.3 W
28.36 mW
91 mW
1800 Logic cells
1602 Logic cells
24
28
Table 3.1 compares ASIC and FPGA Implementations of Huffman decoder. It gives the
Power and area analysis of the design, using Synopsys Design compiler logic synthesizer. The design
has been mapped to 0.6 Micron CMOS Technology. ASIC design methodology adopted for Huffman
decoder design, yields low power dissipation and relatively higher performance.
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6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
3.3 Simulation Results for Text
The functional simulations [7] for the Huffman decoder are carried out using Modelsim tool.
In case of text both encoder and decoder are presented. The decoder requires for decoding the
Huffman encoded data[8].
Fig 3.2 Huffman Encoder output for “HELLO”
Fig 3.2 shows the simulation results for Huffman encoder. In Fig 3.2, address is the input to
LUT, character is the output from the LUT which is to be encoded. Encoding for the character starts
when the enable signal goes high. Cipher is the encoded serial output from the Huffman encoder.
Fig 3.3 Huffman Decoder output for “HELLO”
Fig 3.3 shows the simulation results for Huffman decoder. The encoded data for the text is
input to the decoder, which is applied to the decoder in the form of serial bits.
Cipher is the serial encoder data input. “en” is the enable signal to enable decoding. “plain” is
the decoded character symbol. Fig 3.4 shows the simulation results of the combined unit with both
encoder and decoder.
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7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
Fig 3.4 Huffman Encoder and Decoder combined results for “HELLO” text
In Fig 3.4, “addr” signal is a 5-bit input signal which acts as the address to the LUT
in the encoder stage which gives corresponding alphabetical outputs. “Encode” is the serial output
stream which given as input to the decoder. “decchar” is the decoded character output from the
decoder. The encoding and decoding [9] [10] operations are performed for the text “HELLO”. The
simulation results for “HELLO” text reveal that only 22 bits are required to store it whereas 40 bits
are required for the original text. Hence original data can be retrieved easily and requires less
memory by using the new binary tree algorithm.
4. CONCLUSION
Huffman decoder using Binary tree algorithm was implemented on ASIC and FPGA
platforms. The Architecture implemented by ASIC Design, using 0.6Micron CMOS technology,
yields leakage power dissipation of 33.25nW, dynamic power of 28.36mW, and area containing
1800 logic cells. For FPGA Design (Spartan 2E), the above said parameters are 1.3W, 91mW, and
1602 logic cells respectively. Hence the ASIC Implementation results an architecture that consumes
low power than FPGA design methodology. Future works needs to be carried out to improve the
area.
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8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 6, November - December (2013), © IAEME
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AUTHORS’ DETAIL
VIJAYAKUMAR SUVVARI completed his U.G from SISTAM
Engineering College, Srikakulam Affiliated to JNTUK, in the year 2007 and he
is pursuing M.tech (VLSI System Design) in AITAM College, Tekkali. His
research interests are VLSI Design, DSP etc.
M.V.H. BHASKARA MURTHY received his M.Tech from JNTUH,
Hyderabad in 2006 and B.E from Andhra University, Visakhapatnam in the year
1993. He is pursuing his Ph.D., in the area of Wireless Communications from
JNTUK, Kakinada, India. He is a member of IE (India). He had 20 years of
experience includes both Industrial and teaching. At present he is working as a
Associate Professor in the department of Electronics and Communication
Engineering, AITAM College, Tekkali, Andhra Pradesh, India. He has
published and presented both national and International Conferences and Journals. His areas of
interests are VLSI Design, Wireless Communications etc.
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