Detailed CV.

1. 11 Sept 2011 [TECHNICAL PROJECT MGR / PRINCIPAL ENGINEER]
Horace Sklar Profile
293 N. State College Blvd
Apt #4059 I save you money and time, while reducing risk, by delivering solutions to the most
Orange, CA 92868 complex, time consuming efforts of your projects in new product developments for rapid
prototyping, and proof-of-concept.. I help my clients during most phases of their technical
cell 415.760.6213
projects; proposal writing, systems requirements/analysis, architecture development and
google 415.375.0112
skype horace.sklar hardware board/FPGA/ASIC design, test and integration.
I excel in custom system designs of high-end applications maximizing COTS products from
HoraceSklar@alumni.princeton.edu CompactPCI, VME64x, VPX merchants, based around a common processor blade and
HoraceSklar@alum.mit.edu fabric architectures; with the ultimate form-factor reflecting needs and preferences in
hjsklar@ieee.com mechanical robustness and ecosystem.
My first twelve working years were in Military/Defense organizations. Subsequently, I
started Silicon Technology Labs (STL), a small-disadvantaged-business, focused on
SILICON ASIC/FPGA engineering design services. As sole proprieitor, I honed my skills in the areas
TECHNOLOGY LABS of customer relationshipt, project, and resource management, and augmented my technical
design skills.
CORE
Core competencies in digital image/signal processing and ASIC/FPGA design provided me
COMPENTENCY STL a competitive advantage in highly integrated, high performance processing.
My technical expertise encompasses systems architecture definition and trades, algorithm
development, hardware design, test and integration in Army, Navy, Air Force and satellite
APPLICATIONS & electronics platforms for military communications, digital signal, image, and neural net
PLATFORMS processing, electronic/anti-submarine warfare and includes other areas such as built-in-
test and artificial intelligence.
I performed systems design efforts consisting of requirements collection and flowdown,
SYSTEM analysis, architecture trades, algorithm developments, HW/SW allocations, and ICD
ENGINEERING resulting in system developments. Developed and implemented DO-254 Design
Verificaation Test plans.
I accumulated high-speed board level analog and digital design experience with over fifteen
ASIC/FPGA gate arrays design alternatively using VHDL behavioral and RTL and
ENGINEERING hierarchical schematic based designs using DxDesigner and multi-vendor CAE simulation,
DESIGN test bench, signal integrity, and packaging tools. My embedded processor and firmware
experience spans bit-slice, numerous multi-vendor 16/32-bit micro controllers /
processors, DSP chips, and application specific analog and digital designs.
CAREER SUMMARY
1986- now Silicon Technology Labs, San Diego, CA – sole proprietor / Sr. Electronics Consultant
1983-1986 TRW / Military Electronics & Avionics Div, San Diego, CA - Subproject Manager
1981-1983
ITT / Defense Communications Div, San Diego, CA – Sr Member Technical Staff
Rockwell Intl / Collins Radio Div, Anaheim, CA - Engineering Scientist Level IV
1978-1981
GTE Sylvania, Needham, MA – Research & Design Engineer
1975-1978
EDUCATION
1975 Massachusetts Institute of Technology, EE in Communications, Thesis Open
1972 Princeton University, BSEE (Magna Cum Laude)
1 Copyright 2010 Horace J. Sklar. All rights reserved.

2. Silicon Technology Labs Contract Experience
Silicon Technology Labs  Sole-proprietor of an engineering services firm:
San Diego, CA - Independent Consultant/Contractor (2000 – Now)
SIC: 8711 - Sole-proprietor of up to 10 ASIC engineers, office manager, secretary. (1986 – 2000)
Sole Proprietor  Customer Relationship Management of clients and sales prospects.
(10/86 – Now)  20+ years of experience in the high-speed digitsal design, development, integration, verification test and
certification of safety-and mission-critical systems.
 Create and maintain project and resource schedule, documentation, and act as liaison between all employees and
clients in compliance with company, industry standards.
 Product development of over 1,000 Crunch-860 Image Processor and daughter boards, including financing,
concept, design and integration, and production through life cycle.
 Provide technical direction and training to engineering teams throughout project stages.
 Expertise in conducting design reviews, supervising personnel, estimating labor, establishing schedules, creating
contingency plans, and maintaining budgets.
 Team leader with demonstrated ability to build strong relationships with co-workers.
 Hiring and firing of employees & consultants, training, performance reviews, and raises.
CONTRACTS
Sr. Eng Contractor KC-10 Advanced Boom Control Unit (ABCU) DO-254 Level B: requirements
Macrolink Inc. flowdown/traceability, electronic design, HW Design & Verification Test procedures for
Anaheim, CA
KC-10 Adv Boom Control Unit circuit card test and system integration using LabVIEW™. SubVersion™ control, schematic
capture PADS™ for analog (LVDT, Analog Servo Motor Control, ADC/DAC circuits) and design
and PCB layout support to Actel A3PE FPGA VHDL redesign in a custom VME64x subsystem
using Actel VHDL ProASIC3/E Design Flow.
Sr. Principal Contractor NFIRE satellite payload Lead Hardware design of VME64 Spacecraft Interface using ACT2
SAIC/EVSD RadHard FPGA with MBLT/2eSST transfers, and VME64 Image Processor of target payload
San Diego, CA
Electronics Control Module. DxDesigner with Actel Silicon Explorer II tools.
Sr. Principal Engineer
NFIRE Payload Electronics
Technical Lead Contractor Ground Standoff Minefield Detection System subsystem requirements analysis, develop CAD
Information System Labs methodology and train personnel, architecture development, design, cPCI COTS selection,
San Diego, CA
GSTAMIDS integration, and hardware design of a 6U cPCI™ Data Acquisition Module. Design features
32-bit, 33Mhz PCI Bus-Master Interface with 9-channels DMA, Intel 21154 PCI-PCI Bridge, 8-
channels 12-bit, 10Mhz Rx Data Acquisition with dithering, Dual 20 MHz Tx channels, dual
Intersil 5216, and support of Xilinx Spartan-II FPGAs during I&T. DxDesigner EPD 2.0 tool
suite, Xilinx ISE 4.2, PCI and FIFO IP cores.
Delivered cPCI Subsystem: chassis, DAM 6U, COTS & TIM modules to SW team.
Fourteen month developments to set up HW Dept, train engineers, deliver HW.
Lead Eng & Project Mgr Develop Air Force Research Labs Portable MSTI-3 Payload Simulator. Architect and design of
AF Research Labs portable subsystem and board using two Actel ACT-3 FPGAs that accept three high speed
Phillips Laboratories
Albuquerque, NM video telemetry, command and control, sensors, housekeeping with a PCMCIA interface to
Portable MSTI-3 GFE Simulator laptop and three real-time B&W video outputs. DxDesigner and Actel CAE tools.
Delivered Portable Ground Based Simulator replacing Four 19” Racks
Lead Technical Contractor Miniature Sensor Technology Insertion-3i system architect/ designer for VME32 space-based
SAIC/EVSD payload Electronics Control Module consisting of design, simulation, test and integration of
San Diego, CA three fault-tolerant TMS320C30 camera and Spacecraft Interface PWA utilizing Actel ACT-
MSTI 3 Payload
2/3 FPGA and TI DSP processors. DxDesigner and ACT tools. Vacuum, temperature,
2 Horace Sklar Curriculum Vitae

3. acceptance testing at Edwards AFB.
Edwards AFB I&T, Low Earth Orbit Launch in 1997, One Year Flawless.
Most reliable and successful satellite program in Phillips Labs.
Testbench Developer System Administrator and VHDL benchmark support for three LSI Logic 300K technology
TRW/MEAD ASICs, perform verification VHDL test benches and backend release process simulation, ATP,
Rancho Carmel, CA floor planning and production test vector for ATF program.
ICNIA/INEWS
Program management of 20 ASIC engineers in UNIX CAE environment.
FPGA Designer Design Xilinx 4010 CUE™ FPGA for Air Force Mil Parameter Encoder application, 25 MHz
TRW/MEAD controller with 12K gate density using DxDesigner and Xilinx ICE tools. Performance of 25
Rancho Carmel, CA
Mil Parameter Encoder
MHz required custom floor planning and placement of individual critical path cells at Xilinx
Main office site in Milpitas.
Warfighter Program CUE FPGA design, I&T and doc package release
Design, Product Engineer Lead system engineering for HNC Inc. and evaluation of alternate MIMD and SIMD
Crunch-860 Product massively-parallel neural-net architectures and trade-offs leading to SBIR awards and
Development DARPA contract wins. Architecture study addresses the range from fully hard-wired
physical neural nets to virtual machines using numerous neural net paradigms.
Technology assessments included custom ASIC, FPGA, and DSP based architectures.
Study to identify future architectures of neural net products.
Resulted in concept for Crunch-860 product line.
Led to SBIR Phase I CMP win  ViP daughterboard architecture
4
Led to DARPA Battlefield Neurocomputer SBIR  SNAP™ 1993.
System Architect Internal product development of multi-phased, dual platform (PC & VME) based Image
HNC Inc. Processor PWAs using Intel 80860 with standard I/O daughter cards.
Crunch-860 Accelerator
& IO Products Funded, developed royalty agreement contracts with HNC Inc.
Administration of two board engineers in UNIX environment
Delivered dual platform Crunch-860 boards on schedule
>1000 Crunch-860 sold on royalty
Develop Crunch-860 compatible, dual platform, 48 MB DRAM Memory and DT-Connect™
I/O Interface to enable 3rd Frame Grabbers to complement product line.
Delivered DT-Connect daughterboard IO in 4 months on schedule
st
MEM48 Daughterboard 1 Pass Success
ASIC Lead Vision Image co-Processor (ViP™) Crunch-860 daughterboard consisting of a ViPIO (80K) ASIC
HNC Inc. and ViP (110K) ASIC, LSI Logic 100K foundry. Managed six ASIC engineers developing
Crunch-860 Accelerator
& IO Products
hierarchical VHDL designs with DxDesigner for chip, board level simulations and test benches,
and LSIL MDE tools for timing, placement and verification. ViP ASIC resulted from an SBIR
phase one patented 2D, 8x8 processing element systolic array architecture operating in lock-
step at 30 Mhz. ViPIO provided dual-bank DRAM address generation and pre-fetching, Intel
860 handshaking, and local storage with data descrambling and formatting for the ViP ASIC.
Developed new 4-stage pipelined MultiplierAccumulators (MAC)
Fully simulated both ASICs and board level, used VHDL behavioral and RLT level for improved
simulation speed
3 Horace Sklar Curriculum Vitae

4. VHDL Designer SBIR Phase 1 Proposal effort and win resulting in the VHDL high level definition of two-
HNC Inc. dimensional systolic array architecture of fixed point processing elements for real-time image
Neural Network Architecture
CMP
processing.
VHDL CMP VHDL Specification
Patent Application & Award 1993
System Architect DARPA proposal team win resulting in system specification of a SIMD Army Battlefield
HNC Inc. Neurocomputer and resulting Numerical Array Processor ASIC consisting of a 1-D systolic
SIMD Neural Array Processor
(SNAP) array of 4 arithmetic cells1 in a SIMD ring and SNAP™ board level design of a 6.5 GFLOP
floating-point processor. A 17-bit address bus allows maximum of 522 KB of memory per cell.
LSI Logic ASIC project management and co-design of 300K gate density ASIC.
SNAP made of 4 NAP chips and memory for 4 GBPS IO & 640 MFLOPS
2,3
SNAP won 1993 IEEE Gordon Bell Award for Price/Performance
System Proposal Lead Proposal lead systems engineer for a 32-channel Fast Time Analyzer System (ASW), win
Scientific-Atlanta(Cisco) based on innovative architecture. Efforts included signal processing algorithm
San Diego, CA
Fast Time Analysis System development such as FFT and Polyphase Filters with Matlab™ Simulink and Hardware-
(FTAS) in-the-Loop support, architecture trades with various DSPs (320C30, 56000, and
29000), application specific devices, coding, and system development concepts.
Architecture reduced LRUs from 12 down to a single PWA, 8-stage, loosely-coupled
array of identical DSPs partitioned along data rate requirements via high speed serial IO.
System design and performance using Matlab™ allowed for incremental and
independent debugging of system, software, and hardware from remote sites. Design
firmware code and test on FTAS real-time AT&T 32C™ DSP serial systolic architecture
for ASW acoustic DSP narrowband algorithms. VME test bed with PC-based tools:
Debugger, Simulator, Assembler. Used MATLAB and RTW for algorithm. Develop,
produce 22 FTAS SCSI-2 Disk Array Units utilizing quad 1.6GB disk arrays in a 19" rack.
Innovative Linear Systolic DSP Architecture  Contract Win
Validated Real Time “Hardware In The Loop” Development Methodology
Reduced LRUs from 8 to 1, minimizing life cycle costs and NRE
Released 22 FTAS systems (FQX-3) and DAS chassis on schedule
Principal System Eng Peace Shield Systems Lead analyst for modular, secure-voice/data equipment.
ITT/Defense Communication Architecture consisted of loosely-coupled, multi-site, multi-processors (TMS320C25 DSP
Div
Clifton, NJ
and Harris I/O processor (6303)). Modularity allows for small number of unique
Peace Shield Communication processor and peripheral modules configured into eight separate systems spanning
secure-voice terminals, data and FAX terminals with small number of Line Replaceable
Modules. Design comprehensive BITE system concept.
Developed System Architecture, Allocations, ICDs, Requirements
Completed FMA for Modules
Sr. Software Contractor Senior software engineer for DSP algorithms design, high-level descriptions, ADA PDL
Linkabit Corp (L-3) documentation, C programming (HOL), and assembly code for TMS320C25 DSP. Perform
San Diego, CA
code verification on TI TMS simulator tools in a VAX/VMS environment.
SCOTT Comm Satellite
1
A single NAP chip can perform 160 32-bit MFLOPS.
2
The price/performance category is given to the entry demonstrating the best price-performance ratio as measured in megaflop/s per dollar on a genuine application.
3
HNC’s SNAP was adapted for Navy sonar recognition systems, allowing submarines to process sonar signals and detect underwater objects more efficiently.
4 Horace Sklar Curriculum Vitae

5. EMPLOYERS
Air Force ALQ-131 VTCA Subproject Manager, leading team of fifteen Work Package
Engineering Scientist 4
TRW / MEAD (NGC)
Managers and ASIC/FPGA hardware engineers for hardware/software design and CAE
Rancho Carmel, CA environment incorporating ten ASICs and VHSIC technologies into an electronic warfare
(3/1983 – 10/1986) pod.
st
1 Successful VHSIC Program Integration and Delivery: Congress 1986
Availability Improvements via higher MTBF, reduced MTTR using MADS™
IR&D Principal Investigator for Maintenance and Diagnostic System™ to support generic
VHSIC, ASIC, and off-the-shelf digital & analog technology BIST/BITE. Conceptual
development and design of BIST ASIC to execute pseudo-random generation and
signature-analysis techniques.
st
1 TRW Insertion of BITE, BIST, PRN techniques using integrated architecture
IR&D Rules Expert on Advanced Avionics Availability Improvements program to develop
real-time rule-based Expert diagnostic system to perform fault diagnosis and isolation to
Line Replaceable Unit.
Rule-based Expert System report evaluation on deliverable ALQ-131 VTCA
Redesign AMD 2900 based bit-slice array processor for QAM/QPSK/FSK multimode
modem. Signal Processor team leader for Advanced Tactical Fighter proposals.
Sr. Member Technical Staff System analysis and architecture trades, algorithm development and simulation,
ITT / Defense Communication hardware and software design code for Avionic speech recognition front-end employing
San Diego, CA the TMS32010 DSP and 68000. C-algorithm development on VAX/780 UNIX host for
(1/1981 – 3/1983)
recursive and non-recursive filter-bank and Linear Predictive Coding techniques. Voice
Recognition algorithm designs and provided TI support on hardware design of TMS32010
DSP. Design of C-based TMS32010 Simulator.
Design of Secure Voice terminal consisting of LPC Vocoder and 16-KBPS wire-line
modem. 16KBPS QPSK Wire-line Modem system architecture and hardware design.
Design incorporated custom AMD 29000 bit-slice architecture for real-time signal,
processing and Motorola 68K host embedded processor. Tightly coupled design with
29000 bit-slice executing high level macros. 1st Militarized Secure Voice Terminal with 16
KBPS digital voice quality. Minimized microcode development through bit-slice ISA
architecture. System design engineer on advanced 1990s secure voice YOHO terminal.
Hardware Project Manager Gained important project management skills and interpersonal skills motivating a team
Rockwell International / of ten engineers as a hardware project manager for new HF & UHF modem
Collins Radio Div communications product lines. Develop requirements, design, build and code bit-slice
Anaheim, CA
(8/1978 – 1/1981) array and control I/O processors satisfying throughput of real-time DSP techniques for
LINK-11 (NAVY), TADIL-A, TAOC-85 modes.
Delivered HF modem product line using CMOS/SOS Intel bit-slice technology
Design analog/digital peripherals that will allow, in conjunction with processors,
multitone (QPSK/Kineplex) and adaptive single tone HF in a multimode and simultaneous
mode of operation. Modem features BITE subsystem.
ii
NTDS PWA for parallel I/O and Custom Analog interfaces
5 Horace Sklar Curriculum Vitae

6. Research & Development First commercial design of 5-MHz, 40-bit wide horizontal instruction code 2900 bit-slice
Engineer
GTE Sylvania processor and microcode for multi-mode PSK satellite modem utilizing high-speed analog
Needham, MA front end half-baud integration algorithm.
(6/1975 – 8/1978)
Met schedule and successful showing of product at Washington, DC Air Force show
Hardware lead engineer for Navy secure CVSD communications subsystem. Design and
macro/assembly, and C program of BITE subsystem based on Z80.
EDUCATION
Massachusetts Institute of Communications Major
Technology Course Work: Digital Signal Processing focus
Cambridge, MA
Electronic Engineer Thesis on Automated Microprocessor Controlled Goldman Hemisphere (open)
Princeton University Graduated Magna Cum Laude
Princeton, NJ
BSEE 1972 Accelerated three year graduation award
Magna Cum Laude Focus on Signals & Systems
University of Miami
Special College Program for Gifted Math High School Students
Miami, FL
Undergraduate Study Took six one-semester Mathematics courses.
by Center of theoretical Physics GPA: 4.0
CMDE ASIC Design Workshop, LSI Logic 1992
TRAINING DxDesigner/VHDL Workshop, Viewlogic Corp, Marlboro, MA 1991
Program Management Workshop, TRW 1986
“Embedded expert systems for fault detection and isolation (in avionics
systems)” Smith, Carolyn and Sklar, Horace; Digital Avionics Systems Conference, 7th,
PUBLICATIONS Fort Worth, TX; US; 13-16 Oct. 1986. pp. 613-617. 1986
BiCMOS Technologies Trends, STAP Program, TTG, 1987
32-bit Processors Trends, STAP Program, TTG, 1987
High Technical Performance Award Resulting in Critical Milestone Delivery,
Macrolink Inc. April 2011, Monetary award for exceptional contractor performance on
"Advanced Boom Control Unit" program resulting in meeting customer incentive critical
delivery milestone.
AWARDS &
Patent # US5471627, "Systolic array image processing system and method". Dr.
HONORS
R. W. Means and Horace J. Sklar, Issued 11/28/1995.
“Advanced Avionics Availability Improvements”
TRW IR&D report, 86/85, Project No. 86121026 & 8512026 Advanced
SNAP Design won IEEE Gordon Bell Award in Price-Performance
ARRIVA Award. TRW/MEAD, Sub Project Manager performance excellence for ALQ-131
VHSIC Transmit Control Assembly program.
Mil-Std-1397: NTDS Parallel I/O Centralized Slew Rate Design
Rockwell Trade Secret
Certified SBA Small Disadvantaged Business entity (SDB)
IEEE Member
CLUBS &
Texas Instruments Registered DSP Consultant
ORGANIZATIONS
PCI Industrial Computer Manufacturers Group (PICMG) member (cPCI & VME)
Trilingual: English, Spanish, French
OTHER SECRET clearance (1990 Inactive)
US Citizen, Active US Passport, Willing to Travel & Relocate
6 Horace Sklar Curriculum Vitae

7. 7 Horace Sklar Curriculum Vitae