Defense

Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms Advisor: Lih-Yih Chiou Student: Hi-Ho Chen 23 June 2008

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Introduction ,[object Object],[object Object],[object Object]

Top-down Design Flow [1]S. S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Using TLM for exploring bus-based SoC communication architectures," 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 2005, pp. 79-85, 2005

Arbitration Level vs. Simulation Speed [2]C. Lennard and D. Mista, "Taking Design to the System Level," 2006 [Online]. Available:(http://www.arm.com/pdfs/ARM_ESL_20_3_JC.pdf)

High Level Synthesis ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[3]SPARK. Methodology, http:// mesl.ucsd.edu/spark/methodology.shtml

Contributions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Previous Works - SPARK (1) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[4]SPARK:A High-Level Synthesis Frame work For Applying Parallelizing Compiler Transformations VLSI Design, 2003. Proceedings. 16th International Conference on 4-8 Jan. 2003 Page(s):461 – 466

Previous Works - xPilot (2) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[5]“Platform-Based Behavior-Level and System-Level Synthesis “ International SOC Conference, 2006 IEEE Sept. 2006 Page(s):199 – 202

Previous Works - MFASE (3) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[6]MFASE: Multiple Functions SoCs Analysis Environment the VLSI Desing/CAD Symposium, Taiwan, Augest 2007

Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Representation ,[object Object],[object Object],[object Object],[object Object]

Design Flow Overview 2/2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Block Level ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Block Level - Methodology 1/10 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],for(j=0;j< 2 ;j++){ for(i=3;i< 7 ;i++){ b[j][i] = (a[j][i]+a[j][i+1])>>1; } }

Block Level – Methodology 2/10 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Burst New Transform Read Write

Block Level - Methodology 3/10 ,[object Object]

Block Level - Methodology 4/10 ,[object Object],[object Object],[object Object],[object Object],B(): Burst size T(): Transaction number R: Read from bus W: Write to bus

Block Level - Methodology 5/10 ,[object Object],[object Object],[object Object],B(): Burst size T(): Transaction number R: Read from bus W: Write to bus

Block Level - Methodology 7/10 ,[object Object],[object Object],[object Object]

Block Level - Methodology 9/10 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],2 3 2 4 Write Bus Access times O X O O Boundary Case 4 3 1 Case 1 Read Bus Access times Max Buffer size Irregularity 2 5 1 Case 2 1 2 10 8 2 3 Case 4 Case 3

Block Level - Methodology 10/10 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],O(): operator cycles B(): buffer size R(): Read counts W(): Write counts S(): state sizes Ir(): Irregularity case1 case2 case3 case4

Translation 1/3 ,[object Object],[object Object],[object Object],Example for ”If then else” Example for ”for loop”

Translation 2/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Translation 3/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Platform Level ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Develop Library for CoWare 1/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Develop Library for CoWare 2/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Develop Library for CoWare 3/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],ACT Energy Idle Energy Total energy = (ACT Energy + Idle Energy) Power= (ACT Energy + Idle Energy)/total time Active power/unit time Number of Active counts ,[object Object],Number of Idle counts Idle power/unit time

System Control Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

CoWare - Scalar ,[object Object]

Simple Bus Environment - Scalar SystemC 2.1 Simple bus Read Transfer Write Transfer

CoWare Environment -Scalar ,[object Object],Step 1 Step2 Step3 Step4 Step 5

Experiments – Scalar ,[object Object],[object Object],100638 100638 325296 Cycle time 91775 91775 239761 Approximate time cycle cycle cycle Cr part Cb part Y part scalar Scalar Y part Parallel constrain 4 33388 115118 0 Communication Cycle 1668 31680 1724 81 11 case 3 1403 31680 9916 78 4 case 2 23 126720 0 0 0 Original C code Code Line Computation Cycle Bus Access ST Size Max cascade

Experiments – Power Monitor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Data Path 23.4124 nw 1.0444 mw 8 ADD 21.3216 nW 808.2718 uW 8 SUB 67.5333 nW 4.0100 mW 8 DIV 9.9244 nW 425.8246 uW 8 SHR Size Idle power Active power 66 nw 1.7346mw 32 Buffer 1.7346mw 0.418mw Power power 32 6 width 12 nw FSM 66 nw Register Idle power

Experiments - Scalar ,[object Object],2124065.68 423934 1000 101638 WITH PMU 11000089.08 X X 526572 NO PMU Scalar Cb 11000089.08 X X 526572 NO PMU Scalar Cr 14038522.54 199276 1000 326296 WITH PMU Scalar Y 2124065.68 22584673.08 Power mw 423934 1000 101638 WITH PMU X X 526572 NO PMU Sleep Cycle Wake up Cycle Active Cycle Case 18286653.9mw with PMU 44584851.24mw No PMU 58.98% Scalar Power Saving Rate

[object Object],Experiments - DWT DWT IDWT

Experiments - DWT ,[object Object],Step 1 Step 2 Step 3 Step 4

Experiments - DWT ,[object Object],[object Object],76262 Cycle time 11088 Approximate time cycle DWT DWT Parallel constrain 1 74678 0 Communication Cycle 8630 1584 9504 42 1 case 1 46 1584 0 0 0 Original C code Code Line Computation Cycle Bus Access ST Size Max cascade

Experiments - DWT ,[object Object],2155442.52 68600 1000 76362 WITH PMU 4066501.32 X X 145962 NO PMU DWT IDWT 2105550.72 75362 1000 69600 WITH PMU 4415350.53 X X 145962 NO PMU Power mw Sleep Cycle Interrupt Cycle Active Cycle 4260993.24mw With PMU 8481851.85mw NO PMU 49.765% DWT Power Saving Rate

Conclusions ,[object Object],[object Object],[object Object],[object Object]

Future Works ,[object Object],[object Object],[object Object]

References ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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