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HiPerDevGenTM Accelerates Analog Physical Design
- 1. HiPerDevGen™ - Structure Generation Acceleration of Analog Physical Design
- 2. Factors Driving the need for Analog Acceleration 1 Shorter Product Development Times 2 Shrinking Process Geometries 3 EDA advancement on other areas of M/S Design © 2010 2
- 3. Shorter Product Development Times Average IC Product Development Times Early 1990’s cycle times “We need to re-assess design tools and practices to ensure we 0 6 12 18 24 30 can achieve right first time design in a Today’s average cycle times reasonable timeframe, and thus reach 0 6 12 18 24 30 profitability sooner.” Douglas Pattullo, Director Field Shorter Product Development Times Technical Support, Faster Time to Market TSMC Europe © 2010 3
- 4. Effects of Shrinking Geometries Companies are most concerned about the challenges of higher mask costs, greater design complexity, IP costs and availability, and inadequate EDA tools. Source: Kalypso Semiconductor Analysis 2009. © 2010 4
- 5. Effects of Shrinking Process Geometries Technology Cost Pressures – As geometries shrink, mask and design costs go up Design & Mask Costs $120,000 $6,000,000 TSMC’s wafer forecast shows a 40% CAGR (4x in 5 years) due to new designs in 90nm, 65nm and smaller $100,000 $5,000,000 Design Costs ($k) Mask Costs ($M) $80,000 $4,000,000 $60,000 $3,000,000 First pass silicon is an essential target for all semiconductor $40,000 $2,000,000 companies regardless of geometry $20,000 $1,000,000 $0 $0 0 1 350nm 2 3 4 590nm 6 7 8 9 22nm 10 Geometry nm © 2010 Design Cost Mask Costs Source: EETimes 5
- 6. Effects of Shrinking Process Geometries EDA Trends – Development and support of Design Kits – Hierarchical Verification – Successful deployment of P&R Tools • Can handle multi-million gate designs – Use of greater processing power © 2010 6
- 7. Effects of Shrinking Process Geometries Transistor Count v Design Cycle Time Transistor Count Design Time 250nm 90nm 45nm Design cycle times at 90nm are increasing!! Why?? – Analog Layout Design IS now a bottleneck!! – Acceleration of this process is key © 2010 7
- 8. Analog Design – Bottleneck 1 Full automation approach has not gained traction Analog Automation has been a disappointment Difficult to set up Schematics need to be generated in defined formats Complicated to Constrain 2 Analog designers like to retain control 3 Very difficult to automate analog layout due to the „artistic‟ nature of the process © 2010 8
- 9. Analog Physical Design Automation What do users want? – Create efficient device placements from user-provided constraints – Do this in a matter of minutes – Easy to set-up and use – Compliments existing user environments – Closely resemble handcrafted layout – Allow designers to apply constraints to groups of devices © 2010 Source: Jim Solomon, Founder Cadence 9
- 10. Our Approach Acceleration Differential Pairs Recognition and Generation of Common Current Mirrors Structures Resistor Dividers Closely aligned to handcrafted layout Our Approach Correct by Construction DRC & LVS Clean Guarantees design standards are Consistent High Quality the same across the whole organisation Understands functionality & process Is “Silicon Aware” artefacts Analog Designers can easily tune the Rapid generation and simulation loop design for optimal solution © 2010 10
- 11. Our Solution HiPerDevGen™ Automatic generation of design primitives – Using only set of DRC rules as base input – Reduces manual tasks and accelerates full custom layout No change in design flow methodology Understands design and process requirements associated with each structure – Matching, Parasitics Technology node aware – Devices and structures scale with design rules – WPE, STI/LOD effects on nanometer technologies © 2010 11
- 12. Quick & Easy Set-up Manufacturing Rules User friendly GUI for set-up of new technologies No CAD development required Instant generation of parameterized devices and structures 20 minutes for any new process Note: Tanner will provide technology set-ups free of charge © 2010 12
- 13. Features of HiPerDevGen™ Linear Process Gradients Mask Misalignment Guarantees Implant ShadowingFloorplan Matching PhotolithographicEstimations Invariance Current Flow Direction Antenna / VT Shift WPE HiPerDevGen™ Functionally Layout Aware Optimization User Parasitic Tuning Aware © 2010 13
- 14. Features of HiPerDevGen™ Floorplan Accelerates Layout time Guarantees Estimations Optimized for Yield Matching Double Contacts / Vias Support for DFM HiPerDevGen™ Functionally Layout Aware Optimization User Parasitic Tuning Aware © 2010 14
- 15. Features of HiPerDevGen™ Floorplan Guarantees Estimations Matching Considers device and interconnect parasitics HiPerDevGen™ Optimal solution based on user specific parasitic requirements Functionally Layout Aware Optimization User Parasitic Tuning Aware © 2010 15
- 16. Features of HiPerDevGen™ Floorplan Guarantees Estimations Matching HiPerDevGen™ Ensures user defined matching, parasitic and Functionally requirements performance Layout Reduced Simulation Cycle Aware Optimization User Parasitic Tuning Aware © 2010 16
- 17. Features of HiPerDevGen™ Floorplan Understands functional differences between Guarantees structures Estimations Matching HiPerDevGen™ Functionally Layout Aware Optimizatons User Parasitic Tuning Aware © 2010 17
- 18. Features of HiPerDevGen™ Floorplan Guarantees Estimations Matching Prompt Floorplan Estimation HiPerDevGen™ Functionally Layout Aware Optimization User Parasitic Tuning Aware © 2010 18
- 19. Features of HiPerDevGen™ Floorplan Guarantees Estimations Matching HiPerDevGen™ Functionally Layout Aware Optimization User Parasitic Tuning Aware © 2010 19
- 20. Current Mirror Generation © 2010 20
- 21. Current Mirror Generation © 2010 21
- 22. Current Mirror Generation © 2010 22
- 23. Current Mirror Generation © 2010 23
- 24. Current Mirror Generation © 2010 24
- 25. Current Mirror Generation © 2010 25
- 26. Current Mirror Generation © 2010 26
- 27. Differential Pair Generation © 2010 27
- 28. Differential Pair Generation © 2010 28
- 29. Differential Pair Generation © 2010 29
- 30. Differential Pair Generation © 2010 30
- 31. Differential Pair Generation © 2010 31
- 32. Differential Pair Generation © 2010 32
- 33. Differential Pair Generation © 2010 33
- 34. Typical Op Amp Schematic © 2010 34
- 35. Typical SDL Flow– Op Amp © 2010 35
- 36. HiPerDevGen: Structure Recognition Recognition of Current Mirrors Recognition of Differential Pairs © 2010 36
- 37. HiPerDevGen Generation Generation of Current Mirrors Generation of Differential Pairs © 2010 37
- 38. Completed Op-Amp © 2010 38
- 39. Summary Problem Analog Layout is now a bottleneck Automation attempts have not gained traction Solution HiPerDevGen adopts an acceleration approach Generates high quality “first time right” layout Is “Silicon Aware” and understands process artefacts Gives the user complete control over the design Simple to set-up and use No change in design flow methodology © 2010 39
- 40. Come See for Yourself! View a HiPerDevGen™ Demo Tanner – Booth #1342 Tanner EDA User Event Thursday 17th June 2010 For more information visit www.tannnereda.com © 2010 40