6. Addressing SPI Devices The MCP23S09 is a slave SPI device. The slave address contains seven fixed bits (no address bits) with the read/write bit filling out the control byte.
Welcome to the training module on MCP23S09 - an 8-bit, general purpose parallel I/O expansion for I2C bus or SPI applications with Open-Drain Outputs.
The MCP23S09 is an 8-bit I/O expander with SPI interface operating at 10 MHz. It’s i/o can act as hardware interrupt, with 25 mA source/sink current per I/O. The MCP23X09 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master.
There are two versions of this device. • The MCP23009 – which has an I2C interface and the • MCP23S09 - SPI interface When any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed. When an input state differs from a preconfigured register value (DEFVAL register). The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pin is used to determine the device address.
Here we show SPI interface block which the MCP23s09 implements. It has 11 individual registers which can be adressed through serial interface block. And it can also operate in 2 modes: Byte Mode and Sequential Mode: Byte Mode, stops the automatic address pointer from being inscreaded. Sequential modes enables automatic address pointer increase.
In this diagram, we show how SPI Devices are addressed. It has 8-bits which is a control Byte out of which the first 7-bits represents slave address and the 8 th bit represents whether it is Read or Write operation to be performed to the slave Address it represents.
This slide shows the SPI Addressing Registers and the timing format while addressing the register.
This slides addresses how Interrupt Logic is configured in MCP23S09. The INT interrupt output can be configured as “active low”, “active high”, or “open-drain” via the IOCON register. Each pin is controlled through GPINTEN (Enable/Disable).
Only those pins that are configured as an input (IODIR register) with interrupt-on-change (IOC) enabled (GPINTEN register) can cause an interrupt. Pins configured as an output have no effect on the interrupt output pin. Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP. The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO. The interrupt will remain active until the INTCAP or GPIO register is read. The interrupt condition will be cleared after the LSb of the data is clocked out during a Read operation of GPIO or INTCAP.
This slide shows SPI Input and Output Timing diagram.
Here we show a Typical Performance Curve for Output Valid from Clock Low Tv verses Vdd.
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