3.3 V ECL Programmable Delay Chip MC100EP196
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3.3 V ECL Programmable Delay Chip
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3.3 V ECL Programmable Delay Chip MC100EP196
- 6. ECL Clock Distribution Technique ECL Clock Distribution Tree ECL to TTL Clock Distribution Mixed ECL and TTL Distribution
Hinweis der Redaktion
- Welcome to the training module on MC100EP196. Here we study basic introduction of ECL and its features, Different Distribution techniques.
- The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. programmably It provides variable delay of differential ECL input signals. The EP196 has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
- Emitter-coupled logic (ECL) derives its name from the differential-amplifier configuration in which one side of the diff-amp consists of multiple-input bipolar transistors with their emitters tied together. An input bias on the opposite side of the diff-amp causes the amplifier to operate continuously in the active mode. Consequently, ECL consumes a relatively substantial amount of power in both states (one or zero) but also results in the fastest switching speeds of all logic families. If all inputs are at -1.6 volts (or tied to VEE), the input transistors will all be off, and only the internal differential transistor will conduct current.
- This page gives you information about Logic Diagram of this device. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram. The delay increment of the EP196 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs, All D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0]. The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB).
- In this page we discuss about Emitter coupled logic clock Distribution Techniques. Emitter coupled logic clock distribution illustrates a two level clock distribution tree which produces nine differential Emitter coupled logic clocks on six different cards. The Emitter Coupled Logic In Pico Seconds ( ECLinPS) of the E211 device gives the flexibility of disabling each of the cards individually. An Emitter coupled logic clock driver will be significantly faster than a TTL or CMOS equivalent function. Therefore to de-skew the Emitter coupled logic and TTL signals a delay needs to be added to the input of the Emitter coupled logic device. The value of the delay element would be a best guess estimate of the differences in the two propagation delays.
- This page provides you information and capability of fine Tune feature present in this device. The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate This requirement is easily achieved because a 60 ps additional delay can be obtained over the entire FTUNE voltage range. This extra analog range ensures that the FTUNE pin will be capable even under worst case conditions of covering a digital resolution. There are numerous voltage ranges which can be used to cover a given delay range; users are given the flexibility to determine which one best fits their designs.
- Here we introduce about cascading multiple devices. To increase the programmable range of the EP196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196s without the need for any external gating. Furthermore, this capability requires only one more address line per added E196. Obviously, cascading multiple programmable delay chips will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay.
- Clock skew, the difference in time between “simultaneous” clock transitions within a system, is a major component of the constraints which form the upper bound for the system clock frequency. The skew introduced by logic devices can be divided into three parts: duty cycle skew, output-to-output skew and part-to-part skew. ECL logic technologies offer a number of advantages for reducing system clock skew over the alternative CMOS and TTL technologies. ECL devices provide superior performance in all three areas of skew over their TTL or CMOS competitors.
- The most practical application for EP196 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To de skew multiple signal channels, each channel can be sent through each EP196. One signal channel can be used as reference and the other EP196s can be used to adjust the delay to eliminate the timing skews. Nearly any high−speed system can be fine tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances using the available FTUNE pin.
- Thank you for taking the time to view this presentation on “ MC100EP196” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the OnSemiconductor site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit Element 14 e-community to post your questions.