Gated Clock & Design Ware Handling On FPGA Prototype Platforms

1. Gated Clock & Design Ware Handling On FPGA Prototype Platforms Einav Shmaryh Texas Instruments

2. Agenda Introduction TI Overview TI Design Challenges Summary

3. Introduction Texas Instruments WCS design connectivity solutions for the cellular market: Bluetooth, WLAN, GPS, GNSS, NFC and FM Motorola Droid XGPS, WLAN, Bluetooth®,FM RIMPlaybook GPS, WLAN, Bluetooth®,FM Nokia C7 GPS, WLAN, Bluetooth®,FM LGEUptimus3D WLAN/Bluetooth®

4. FPGA Prototype – Targets At Speed RF connection to the FPGA, FPGA prototype designs work at speed (ARM Cortex M3 at 80MHz). The FPGA platform is connected to an RF device which performs: GPS fix location from a satellite at real time WLAN AP link or Bluetooth wireless Real time FW development & Debug before Tape Out Real time FW/HW integration before Tape Out Enables the ability to demonstrate the ASIC chip 2-3 weeks after chip arrival (with ROM base solution) with mature FW

5. TI FPGA Design Complexity Includes 7 different CPUs (ARM 7, Cortex M3) Multiple paths with more than 100 logic levels between FFs Multiple clock dividers (dynamic & static) => needs to be synchronize Multiple Interfaces which include RF (BT=> wireless, GPS => to the satellite) Usage of multiple Design Wares Dynamic power switching Real Time - Close timing up to 80MHz

6. Design Challenges Moving Toward FPGA Our Design encountered 3 main challenges: FPGA vs. ASIC - Clock Tree Design Ware Implementation in FPGA FPGA Flow

7. FPGA Vs. ASIC - Clock Tree TI ASIC Design includes clock dividers, some with constant divider value and some with dynamic divider value, after each divider there is a new clock tree For higher frequency achievement and to eliminate clock skew there is a need for a minimum number of clocks, For this reason we used a “fix gated clock” option. Uses of Synplify tool with “fix gated clock” option can solve only the constant divider value, the tool “knew” the divider value and mapped it to the FF data or CE. Fixing the dynamic divider value there is a need to add dedicated RTL with the uses of the “fix gated clock” option (there is no tool that can guess the divider value)

8. FPGA vs. ASIC - Clock Tree The next figure shows RTL with constant divider value & with Synplify“fix gated clock” option.

9. FPGA Vs. ASIC - Clock Tree With dynamic divider value , Synplify Implementation breaks the clock tree and, now, the clocks are no longer aligned (there is no Synthesis tool that can “guess” the divider value)

10. FPGA vs. ASIC - Clock Tree Uses dedicated RTL with the “fix gated clock” tool option to solve the dynamic divider value clock tree

11. FPGA Vs. ASIC - Clock Tree Synplify Implementation , Fix the clock tree.

12. Advantages: With one clock the tool can close higher frequency Eliminate clock skew Better turnaround time Simplify the constraints Less RTL changes (all the “swallow” RTL is in the ASIC RTL) Disadvantage: 1. The clock duty cycle has changed - might create timing path if using falling edge => theseclocks need special code (fall detected) FPGA Vs. ASIC - Clock Tree

14. Equivalent RTL substituted from built-in library

15. Mapped to FPGA just like other RTL

16. True DesignWare components used if available (& licensed)

18. Design Wares 2. FixGated Clock with DW Use of Fix Gated Clock option with DW “breaks” the clock tree (add BUFG) in the DW clock start point RTL view with the same example (changing one FF to DW) Net list view

19. FPGA Flow To achieve best timing closure and fast turnaround time: Minimize design changes in the original RTL code for FPGA Educate RTL designers to write RTL “FPGA friendly” (e.g. add “ifdefs” in the RTL with extra pipe or changed clocks …) Participate in ASIC architecture from the start to understand how the FPGA can emulate the design better Scripts-based working flow to avoid editing bugs and faster turnaround time

20. Summary For constant clock dividers the Synplify tool (with “fix gated clock” option) fixes the clock tree to one clock and clock enable 2. For dynamic clock dividers a special RTL “hook” is needed (with “fix gated clock” option) 3. For best timing closure, the DW must synthesize with Synplify Premier tool 4. DW with Synplify Premier is more FPGA “friendly” 5. FPGA flow

21. Q&A

22. THANK YOU

23. Back up

24. TI FPGA Platform

25. Design Consideration Minimize design changes in the original RTL code for FPGA Educate RTL designers to write RTL “FPGA friendly” (e.g. add FPGA_mode in the RTL with extra pipe or changed clocks …) Participate in ASIC architecture from start to understand how the FPGA can emulate it better and add FPGA hooks to architecture Scripts based working flow (on the FPGA tools like Synplify & ISE) to avoid manual editing bugs and faster turnaround time On chip debug capability

26. Retentions Flip – Flops TI SOC design uses retentions Flip – Flops , Explain : retentions FF are special FF cell’s in ASIC that do not go to default value in Power down, they save their last value. This option allow the IP to “sleep” during other tasks and to save current.

27. Retentions Flip – Flops FPGA design do not have those cell’s so an RTL hack needed for allow this option in FPGA. Advantage : In the RTL Stage the SOC & FPGA Design Identified all the RET FF and write FPGA Friendly RTL code The ASIC synthesis the FPGA_MODE block as output ‘0’ so there is no logic added for FPGA uses Can be verified (for ASIC & FPGA) via ASIC synthesis tools

28. Design Wares in FPGA 2. Clock gated When using a DW with a divider clock (constant or dynamic ) with icgcell , The tool “brake” the clock tree (add BUFG) in the DW clock start point. To Avoid it, RTL must be change to insert original clock (no dividers) to the DW RTL View

29. Design Wares in FPGA Technology View