The optimization techniques for integrated circuit (IC) layout design are important. IC layout is an inevitable stage of designing before manufacturing. There are many applications which are directly related with layout optimization in practice, such as floor plan for very-large-scale integration (VLSI) design, placement for printed circuit board (PCB) design, packing for logistics management, and so on. As product size keeps shrinking, product lifecycle keeps shortening and product complexity goes up, more electronic components will be integrated into a smaller IC chip or PCB with higher density and shorter time to market. At the same time, multi-objective optimization is common for IC/PCB layout in real product design, so another difficulty is the trade-off between conflicting objectives, such as low power and high performance. In order to improve the best cases and mitigate the worst cases of IC/PCB layout, it becomes increasingly critical and urgent to improve the quality of solution and reduce run time. Simulated Annealing is one of the most popular ways to improve the quality of solution. But the effectiveness to improve solution quality and reduce run time is quite limited due to huge solution space and complex solution distribution.

1. Layout of Integrated circuits using Simulated
Annealing

2.  It is a technique for combinatorial optimization
problems, such as minimizing functions of very
many variables.
 Because many real world design problems can be
cast in the form of such optimization problems,
there is intense interest in general techniques for
their solution.

3.  It is motivated by an analogy to the statistical
mechanics of annealing in solids.
 Heat the solid state metal to a high temperature
and cool it down very slowly according to a specific
schedule.
 SA techniques use an analogous set of controlled
cooling operations for nonphysical optimization
problems, transforming unordered solution into a
highly optimized, desired solution.

4.  If the heating temperature is sufficiently high to
ensure random state and the cooling process is
slow enough to ensure thermal equilibrium, then
the atoms will place themselves in a pattern that
corresponds to the global energy minimum of a
perfect crystal.

5.  Step 1: Initialize – Start with a random initial placement.
Initialize a very high “temperature”.
 Step 2: Move – Perturb the placement through a defined
move.
 Step 3: Calculate score – calculate the change in the score due
to the move made.
 Step 4: Choose – Depending on the change in score, accept or
reject the move. The problem of acceptance depends on the
current “temperature”.
 Step 5: Update and repeat– Update the temperature value by
lowering the temperature. Go back to Step 2.

6. Algorithm SIMULATED-ANNEALING
Begin
temp = INIT-TEMP;
place = INIT-PLACEMENT;
while (temp > FINAL-TEMP) do
while (inner_loop_criterion = FALSE) do
new_place = PERTURB(place);
ΔC = COST(new_place) - COST(place);
if (ΔC < 0) then
place = new_place;
else if (RANDOM(0,1) > e-(ΔC/temp)) then
place = new_place;
temp = SCHEDULE(temp);
End

7. Greedy Algorithm
gets stuck here!
Locally Optimum
Solution.
Simulated Annealing explores
more. Chooses this move with a
small probability (Hill Climbing)
Upon a large no. of iterations,
SA converges to this solution.
Initial position
of the ball

8.  Inefficient global search: In order to assure a final
convergence effectively, the moving methods with
relatively small changes should be used, so the
global search within a short runtime is quite
limited.
 Informational waste: It does not use the
information of past experience, including past
solutions and past moves.

9.  The optimization techniques for IC layout design are
important. IC layout is an inevitable stage of designing
before manufacturing.
 As product size keeps shrinking, product lifestyle keeps
shortening and product complexity goes up, more
electronic components will be integrated into a smaller
IC chip or PCB with higher density and shorter time to
market.
 The applications include floor plan for VLSI design,
placement for PCB design, packing for logistics
management and so on.

10.  By overcoming the mentioned shortcoming, we can
implement mixed simulated annealing(MSA) to
speed up traditional simulated annealing (SA) and
2-stage SA.
 The basic idea is to improve the global search
ability and to speed up the search process by a
special crossover operator, which uses the
information of past solutions.

11.  The crossover operator uses the part of the
configuration to fond out the current best and
reduces informational waste.
 Moreover to improve inefficient global search, a
two-stage algorithm is considered. Rough search
tends to big changes to improve global search
ability while focusing search tends to small
changes to get final convergence.

12.  In summary, the optimization techniques for
integrated circuit (IC) layout design with large
solution space are facing big challenges to get
better solution quality with less runtime.
 A new SA based approach, named MSA could be
implemented to solve three layout design
problems, 2D packing, 2D placement and 3D
packing.
 MSA reduces computational runtime with the better
solution quality and a near log-linear trend of
average improvement rates from SA to MSA.

13.  DEVI ARCHANA DAS
 A4717210017
 2010-2015
 AISST