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QCRYPT Secure High-Speed Communication based on  Quantum Key Distribution
What is quantum communication ,[object Object],[object Object],[object Object],Alice Bob
What is quantum communication ,[object Object],photon splitter detectors The photon explores both paths Quantum randomness Quantum nonlocality (entanglement)
Used daily by some Swiss banks Spin-off from the University of Geneva, 2001 67 km
The QCrypt Concept 100 Gb/s 1 Mb/s OTP High-speed  Q uantum Key Distribution (1.25 Gbps pulse rate)  + 40 – 100Gbps en CRYPT ion  +   WDM Secure high-speed communication for the 21 st  century
[object Object],[object Object],[object Object],[object Object],Q uantum Key Distribution Coherent-One-Way (COW) scheme
Optical scheme:  coherent one way
Pulse generation High-Speed Intensity modulation 250 ps  T fwhm =138 ps
Rapid sine-gating single photon counter Short gates (100 ps) Low noise and afterpulsing High count rates (10 MHz) Rapid gating detector
AES-GCM Encryption ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],How to reach 100 Gbps
AES-GCM Encryption ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],How to reach 100 Gbps
AES-GCM Encryption ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],How to reach 100 Gbps
AES-GCM Encryption ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],How to reach 100 Gbps
AES-GCM Encryption Performance of Encryption core Resource usage in target FPGA ALM = adaptive logic module (2 Flipflops /  1 8-Input Lookup  Table / 2 Adders) AES AES-GCM Target  Max. Frequency 250 MHz 220 MHz 200 MHz Max. Throughput 128 Gbps 112 Gbps 102 Gbps AES AES-GCM Stratix IV GT Logic usage 10 kALM 30 kALM 212 kALM Block Rams (9kbit blocks) 322 322 1’280
100Gbps Interface User side : 10 x 10Giga Ethernet channels through 10 SPF+ optical modules Client side : 1 x 100Gbps channel using WDM optical module feeds with 10 high-speed serial links @ 10Giga All synchronization and channels splitting made into the FPGA FPGA Design
100G Fast Encryption Board PCB:  24 layers, 52 high-speed serial links, 10 power supplies  FPGA main power supply : 0,95V @ 40Amp Communication links: 8x SFP+ & 2x XFP @ 10Giga 1x CXP & 1x CFP @ 100Giga 22x High-speed serial @ 6.5Giga
Case 19 '' and 4U with embedded PC  Hardware (24 layers) with a FPGA (1932 balls)  1 to M  Network Ports Ethernet  1/10/40/100 G 1 to N  Local Ports Ethernet  1/10/40/100 G FC 1/2/4/8/10 Key Manager with Quantum and/or Conventionals Keys 1 to M  Network Ports Ethernet  1/10/40/100 G 1 to N  Local Ports Ethernet  1/10/40/100 G FC 1/2/4/8/10 enCryptor  First tests for the  encryption hardware at start of 2011!  Software VHDL  enCryption Highlights
Conclusions ,[object Object],[object Object],[object Object]

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QCrypt

  • 1. QCRYPT Secure High-Speed Communication based on Quantum Key Distribution
  • 2.
  • 3.
  • 4. Used daily by some Swiss banks Spin-off from the University of Geneva, 2001 67 km
  • 5. The QCrypt Concept 100 Gb/s 1 Mb/s OTP High-speed Q uantum Key Distribution (1.25 Gbps pulse rate) + 40 – 100Gbps en CRYPT ion + WDM Secure high-speed communication for the 21 st century
  • 6.
  • 7. Optical scheme: coherent one way
  • 8. Pulse generation High-Speed Intensity modulation 250 ps  T fwhm =138 ps
  • 9. Rapid sine-gating single photon counter Short gates (100 ps) Low noise and afterpulsing High count rates (10 MHz) Rapid gating detector
  • 10.
  • 11.
  • 12.
  • 13.
  • 14. AES-GCM Encryption Performance of Encryption core Resource usage in target FPGA ALM = adaptive logic module (2 Flipflops / 1 8-Input Lookup Table / 2 Adders) AES AES-GCM Target Max. Frequency 250 MHz 220 MHz 200 MHz Max. Throughput 128 Gbps 112 Gbps 102 Gbps AES AES-GCM Stratix IV GT Logic usage 10 kALM 30 kALM 212 kALM Block Rams (9kbit blocks) 322 322 1’280
  • 15. 100Gbps Interface User side : 10 x 10Giga Ethernet channels through 10 SPF+ optical modules Client side : 1 x 100Gbps channel using WDM optical module feeds with 10 high-speed serial links @ 10Giga All synchronization and channels splitting made into the FPGA FPGA Design
  • 16. 100G Fast Encryption Board PCB: 24 layers, 52 high-speed serial links, 10 power supplies FPGA main power supply : 0,95V @ 40Amp Communication links: 8x SFP+ & 2x XFP @ 10Giga 1x CXP & 1x CFP @ 100Giga 22x High-speed serial @ 6.5Giga
  • 17. Case 19 '' and 4U with embedded PC Hardware (24 layers) with a FPGA (1932 balls) 1 to M Network Ports Ethernet 1/10/40/100 G 1 to N Local Ports Ethernet 1/10/40/100 G FC 1/2/4/8/10 Key Manager with Quantum and/or Conventionals Keys 1 to M Network Ports Ethernet 1/10/40/100 G 1 to N Local Ports Ethernet 1/10/40/100 G FC 1/2/4/8/10 enCryptor First tests for the encryption hardware at start of 2011! Software VHDL enCryption Highlights
  • 18.