1. An Overview of Serial ATA Technology Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email_address]
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10. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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15. Out of Band Signal Forms COMRESET / COMINIT COMWAKE 106.7 ns 106.7 ns 106.7 ns 320 ns
16. Out of Band Signaling Protocol COMRESET COMWAKE COMINIT COMWAKE Host Device
17. SATA Port Model Clock & Data Recovery Serializer Deserializer Analog Front End OOB Detect COMRESET / COMINIT COMWAKE Data Out RX Clock Port Control Logic Tx Clock Align Generator Data In Phy Reset Phy Ready Slumber Partial SPD Mode System Clock SPD Select Tx + Tx - Rx - Rx +
18. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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22. CRD+ & CRD- Encoded Characters 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 8b Character 0x3F This 10b Character transmitted when CRD negative This 10b Character transmitted when CRD positive This character 6 ones 4 zeros Disparity +2 This character 4 ones 6 zeros Disparity -2
37. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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40. FIS types D H Data 46h D H PIO Setup 5Fh D H BIST Activate 58h D H DMA Setup 41h D H DMA Activate 39h D H Set Device bits A1h D H Register transfer device to host 34h H D Register transfer host to device 27h Direction Description FIS TYPE CODE
41. Register – Host to Device FIS Reserved Reserved Reserved Reserved Dword 4 Sector Count Sector Count Reserved Control Dword 3 Sector Number Cyl Low (exp) Cyl High (exp) Features (exp) Dword 2 Sector Number Cyl Low Cyl High Dev/Head Dword 1 FIS TYPE (27h) Reserved Command Features Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
42. BIST Activate FIS T - Far end transmit only – transmit Dwords defined in words 1 & 2 A - No ALIGN transmission (valid only with T) S - Bypass scrambling (valid only with T) L - Far end retimed loopback with ALIGN insertion F - Far end analog loopback P - Transmit primitives defined in words 1 & 2 of the FIS R - Reserved V - Vendor Unique Test Mode – other bits undefined Data [7:0] Data [15:8] Data [23:16] Data [31:24] 2 Data [7:0] Data [15:8] Data [23:16] Data [31:24] 1 FIS Type 58h Reserved [ TASLFPRV ] Reserved 0 Byte 0 Byte 1 Byte 2 Byte 3
43. Data FIS Dword N . . . Dword 2 N Dwords of Data Minimum 1 Dword Maximum 2048 Dwords Dword 1 FIS TYPE (46h) Reserved Reserved Reserved Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
44. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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