Digitalfundamentals chap7

Digital
Fundamentals
Tenth Edition

Floyd

Chapter 7

© 2009 Pearson Education, Upper PearsonRiver, NJ 07458. All Rights Reserved
© 2008 Saddle Education
Floyd, Digital Fundamentals, 10th ed

• Logic circuits
– Combinational Circuits
– Sequential Circuits

Basic Block Flip-Flops

2 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Flip-Flop

能够存储 1 位二值信号的基本单元电
路发器的功能：形象地说，它具有“一触即发 ”的功能。
触
在输入信号的作用下，输出能够从一种状态 ( 0 或
1 ) 转变成另一种状态 ( 1 或 0 ) 。
触发器的特点：有记忆功能的逻辑部件。输出状态不
只与当前的输入有关，还与原来的输出状态有关
。
触发器的分类：
Bistable Monostable
按其稳态工作状态分：双稳态触发器、单稳态触
发器、无稳态触发器（多谐振荡器）；
Astable

CHAPTER OVERVIEW
 Bistable devices have two stable states, called SET and
RESET. They are used as storage devices.
 Monostable devices (monostable trigger, one-shot) have
one stable state. They are used as timers.
 Astable devices (multivibrator) do not have stable state.
They are used as waveform generators.


8-1 LATCHES( 锁存器 )

• A latch is a type of bistable logic device.
一种双稳态临时存储设备，和触发器类
似，只是改变状态的方式有所不同。

• There are two types of latches:
– S-R latch ( SET-RESET latch)
– D latch (Delay latch)


The S-R Latch
 An active-HIGH input S-R latch is formed with two cross-
coupled NOR gates.
 An active-LOW input S-R latch is formed with two cross-
coupled NAND gates.


Negative-OR Equivalent of the NAND gate S-R Latch


基本 S-R 锁存器

稳态情况下，两输出互补
交叉反馈
Q Q 两个输出端

两个输入端
R S

正是由于引入反馈，才使电路具有记忆功能 !
Active-LOW input

输入 R=0, S=1 时置“ 0” Reset
若原状态： Q = 0 Q =1 ！： Q = 1 Q = 0
若原状态

Q 1 0 Q Q 0 1 Q
1 0 1 0

0R 0 1 S1 0R 1 1 S1
输出仍保持输出变为：
： Q=0 Q=1 Q=0 Q=1


输入 R=1, S=0 时置“ 1” Set
若原状态： Q = 0 Q = 1 ！
若原状态： Q = 1 Q = 0

Q 1 0 Q Q 0 1 Q
0 1 0 1

1R 1 0 S0 1R 1 0 S 0
输出变为：输出保持：
Q=1 Q=0 Q=1 Q= 0

输入 R=1, S=1 时保持！

若原状态： = 1 Q = 0
Q 若原状态： Q = 0 Q = 1

Q 0 1 Q Q 1 0 Q
0 1 1 0

1R 1 0 S1 1R 0 1 S 1
输出保持原状态输出保持原状态：
：
Q=1 Q=0 Q=0 Q=1

输入 R=0, S=0 时
Q 1 1 Q
R 0

0
S
Q 1

0R S 0 Q 1

输出：全是 1

注意：当 RD 、 SD 同时由 0 变
为 1 时，翻转快的门输出变
为 0 ，另一个不得翻转。因此
，该状态为不定状态。
不定

基本 S-R 锁存器的功能表 ( 特性
表)
R S Qn Qn+1
置位端
1 1 Qn Qn 保持原态S S Q
0 1 Qn 0
R R Q
1 0 Qn 1 复位端
0 0 0 1*
次态不定逻辑符号
0 0 1 1*

Qn+1 S R
特性方程 Qn 0 0 1 1
n+ 1
Q = S + RQ n 0 0 1 11 1 0 00
*
S + R = 1 约束条件
· 0 1 1 1 1 0
*
Floyd, Digital Fundamentals, 10 ed
th

Q Q R S Qn Qn+1
置位端 0 0 Qn Qn
S S Q 0 1 Qn 1
R R Q 1 0 Qn 0
复位端 1 1 0 0*
1 1 1 0*
R 逻辑符号S
Active-HIGH input
特性方程
Qn+1 S R
n+ 1 Qn 0 0 1 1
Q = S + RQ n
0 0 0 1
0 1
×
0 0
1
S⋅R= 0 约束条件 *
×
1 1 0 0 1
*

应用：机械开关的防抖动

S

R

Q


74LS279 四重 S-R 锁存器


Example 8 - 1


The Gated SR Latch


S =1
R=0
Q Q S=0 0
S =×
1 R=0
R=×
S=0
R=1
状态转换图

R
1 S
1 门控 S-R 锁存器特性表
同基本 S-R 锁存器
EN R S Qn+1

输出保持原
0 × × 态 Qn
R S
1 0 0 Qn
EN 1 0 1 1
10
Q n+ 1 = S + RQ n 1 1 0 0

SR = 0 约束条件
1 1 1 1*

例：画出门控 S-R 锁存器的输出波形。假设 Q 的初始状态
为 0。

Set Keep
Reset Keep 使输出全为 1

EN 保持原态

R 0 10 0 1
EN 撤去后
S 1
00 状态不定
0 1
Q 1 0 保持 1

Q

The Gated D Latch
门控 D 锁存器特性表
Q Q
D EN Qn+1
× 0 Qn
1 1 1
0 1 0

D Q
EN D EN
Q
Q n+ 1 = D + RQ n
S DQ n
逻辑符号
SR = 0 约束条件

Example 8 - 3


74LS75 Quad Gated D Latches


Latch vs. Flip-Flop

• Bistable devices

• Latch: change output at any time

• Flip-Flop:
– Synchronous
– CLK
– Trigger

8-2 EDGE-TRIGGERED FLIP-FLOPS

• Edge-triggered flip-flops are synchronous bistable
devices. Their outputs change states only at a specified
point on a signal called clock (CLK).


The Edge-Triggered S-R Flip-Flop


Example 8 - 4


A method of Edge-Triggering

S
Q

CLK
Q
R

CLK

如果在脉冲的下跳沿触发，如何实现？

The Edge-Triggered D Flip-Flop


Timing diagram

CP
D
Q

Truth Table
CP D Q Q
↑ D D D

Example 8 - 5


Edge-Triggered J-K FF

S
J
Q

CLK
Q
K R

S = JQ n
Q n + 1 = S + RQ n
SR = = JQ +约K + Q )Q
n n n
R = KQ
n
0 ( 束条件
= JQ + KQ n n


①IF J=1,K=0,Q0=0;THEN G1 enabled, Q=1 (SET)
②IF J=0,K=1,Q0=1;THEN G2 enabled, Q=0 (RESET)
③IF J=0,K=0; THEN no change
④IF J=1,K=1; THEN change to opposite
state(Toggle)


J =1
K=× J K CLK Qn+1
J=0 J0 Q 1 J =×
K=× K=0 0 0 × Qn
C J =×
K K = 1Q 0 1 ↑
↓ 0
JK 触发器的状态
转换图
1 0 ↑
↓ 1
Q n+1
= JQ + KQ
n n
n
1 1 ↓
↑ Q

CP
J 1 0 0 1
K 0 1 0 1
Q

Example 8-6


Example 8-7


Asynchronous Preset and Clear Inputs

Before operation, a flip-flop must have a known
state. This is done by preset ( direct set) and clear
(direct reset) inputs. These are inputs that affect the
state of the flip-flop independent of the clock.


J-K Flip-Flop with Preset and Clear Inputs

PRE 0

J
1Q

CLK
1 0
K 0 1 Q

CLR 1
J S Q
C
当异步置位或复位输入端出现有效
K R Q 电压信号，则不管 J 、 K 端输入如
何，触发器被立即置位（ 1 ）或复
40 © 2009） Education, Upper Saddle River, NJ 07458. All Rights Reserved
位（ 0
Pearson

Example 8-8


IC Flip-Flops--74HC74 (dual D FF)


IC Flip-Flops--74HC112 (dual JK FF)


Example 8-9


Comparison of edge-triggered and level-triggered

E/CP

D

Q(LEVEL)

Q(EDGE)


“ 空翻”现象 EN
Q Q Qn=0
=1
Q
0
1
=0
Qn+1=1

脉冲宽度不合适
时，可能会产生
RD SD “空翻”现象。
0
1 1
0
归纳：在 EN ＝ 1
1 0
1 期EN
间，次态 Qn+1 必
0
R S 然是对原态 Qn 的否
EN Q
定 !


1 Q n + 1 = JQ n + KQ n
J S Q
= 1 ×Q + 0 ×Q
n n
C
K R Q
=Q
n
1

脉冲宽度的变化，
Q
不会导致“空翻”
Q
。


8-3 MASTER-SLAVE FLIP-FLOPS

Master-slave flip-flops are pulse-
triggered.
A master-slave flip-fop consists of two
gated latches.
Data are entered into it at the leading
edge of the clock, but the output does not
reflect the input state until the trailing
edge.
Master-slave flip-flops have largely been
replaced by the 48
edge-triggered devices.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

The Master-Slave J-K Flip-Flop


JK 触发器的工作原理
： Q Q 保持原态
J=K=0 时：
Q Q
F从
R2 C S2
主触发器被
封锁，保持 CP
原态
F主
R1 C S1

=0 K CP J =0

J=K=1 时： 1 Q Q Qn=1 时
0
Qn+1=0
Q Q
F从
R2 C S2

1 CP 0
F主
R1 C S1
1 0

=1 K CP J =1

J=K=1 时： 0 Q Q Qn=0 时
1
Qn+1=1
Q Q
F从
每来一个脉 R2 C S2
冲输出翻转
一次，具有 0 CP 1
计数功能。
F主
R1 C S1
0 1

=1 K CP J =1

J=1 ， K=0 时 Q Q Qn=0 时
1
：
Qn+1=1
Q Q
F从
R2 C S2

CP 1
F主
R1 C S1
0 1

=0 K CP J =1

Q Q Qn=1 时
J=1 ， K=0 时：
Qn+1 =1
Q Q
F从
F 主被封， R2 S2
C
保持原态
CP

F主
0 R1 C S1 0
1 0

=0 K CP J =1

J=0 ， K=1 时： Q Q Qn+1=0

Q Q
F从
R2 C S2
同样原理：
CP

F主
R1 C S1

=1 K CP J =0

Example 8-10


8-4 Flip-Flops Operation Characteristics

• Propagation delay times
• Set-up time
• Hold Time
• Maxim Clock Frequency
• Pulse Widths
• Power Dissipation


Propagation delay times


Set-up time


Hold Time


Other parameters

• Maxim Clock Frequency
• Pulse Widths
• Power Dissipation


Comparison of typical FFs


8-5 FLIP-FLOP APPLICATIONS

• Flip-flops are building blocks for sequential
logic. There are many applications of flip-
flops. For example, by using n flip-flops,
we can achieve
– An n-bit parallel data storage

– A frequency divider of 2n

– A modulo 2n counter

4-bit Register Used for Data Storage
• The data on the D inputs are stored simultaneously by
the flip-flops on the positive edge of the clock.


Divide-by-2 Device
• When a pulse waveform is applied to the clock input,
the Q output is a square wave with one-half the
frequency of the clock input.


Divide-by-4 Device
• When a pulse waveform is applied to the clock input,
the Q output is a square wave with one-half the
frequency of the clock input.


Modulo 4 Counter

• If we take QA as the LSB and QB as the MSB, a 2-bit
sequence is produced as the flip-flops are clocked.


Q0 Q1
1 J0 1 J1
CLK Qn+1=JQn+KQn=Qn
K0 K1

CLK f

Q0 0 1 0 1 0 1 0 1 0 二分频

Q1 0 1 1 0 0 1 1 0 0 四分频

Q1 Q0 n 个触发器可以实现 2n10
00 11 分频 01
Modulo 4 Counter
2n 2 位二进制减法计数器
n

Schmitt-Trigger

• 普通门电路的电压传输特性曲线

工作区： AB 段（截止区） UI<0.6V UO=UOH
DE 段（饱和区） UI>1.5V UO=UOL
线性区： BC 段 0.6V<UI<1.3V UI UO
转折区： CD 段 1.3V<UI<1.5V UI Upper Saddle River, NJ 07458. All Rights Reserved
UO
th
71 © 2009 Pearson Education,

1. 施密特触发器 Schmitt-Trigger

a special type of bi-stable device that has two
特点：
threshold voltages
(1) 输入信号上升和下降过程中电路状态转换对应的的触
发电平不同； (2) 输出信号的边沿很陡。

应用：波形变换、脉冲整形、脉冲鉴幅、构成多谐振荡器
(1) 可将边沿变化缓慢的波形整形为边沿陡峭的波形；
(2) 可将加在矩形脉冲高、低电平上的噪声有效地消除。
R2
两级 CMOS 反相器构
成的施密特触发器：
R1 vo1
vI vo
v′
I G1 G2
′
vo

回顾：
MOS 管

CMOS logic uses the MOSFET in complementary
pairs as its basic element. A complementary pair uses
both p-channel and n-channel enhancement
MOSFETs


CMOS Inverter

HIGH
LOW
LOW
HIGH


R2

R2 VT+ R1 vo1
v ′ = VTH
I ≈ VT + vo 0
R1 + R2 vI v′
I G1 G2
VTH
′
vo
G1 、 G2 的 VTH ≈1/2VDD R1<R2 vo1

当 vI= 0 时 vO= vOL≈0, v'I ≈ 0
v'I
当 vI 从 0 逐渐升高并达到 v'I = VTH 时， threshold折区
Positive-going G1 进入转 voltage
vO1 vO 正向阈值电压：
v′
I
R1 + R2  R1 
VT + = VTH =  1 +  VTH
R2  R2 
正反馈使得电路状态迅速翻转为 vO= vOH ≈ VDD

R2

R1 vo1 VDD
VT- vo
vI v′
VTH G1 G2
I

′
vo
当 vI 从高电平逐渐下降并达到 v'I = VTH 时， v'I 的下降引
发又一个正反馈过程
v′ vO1 vO
I
电路状态迅速翻转为
vO= vOL ≈ 0
R1
v ′I = VTH ≈ VT − + (VDD − VT − )
Negative-going threshold voltage R1 + R2
2VTH
R1 + R2 R1  R1 
负向阈值电压： VT − = VTH − VDD =  1 −  VTH
R2 R2 R2 All
© 2009 Pearson Education, Upper Saddle River, NJ 07458.  Rights Reserved

th
76

vO R1 R2
→ 2 VTH ←
R2
R1 vo1
vI vo
v′
I G1 G2
′
vo

′ R1
O VT + VDD vI vO → 2 VTH ←
VT − VTH R2

输入输出同相

回差电压
R1
v I ∆ VT = VvO − VT − I= 2 R VTHO′ O
T+ v v
2 VTH VDD vI
77 反相输出
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

30kΩ
CMOS 反相器
10kΩ vo1
vI vo VDD = 15V
v′
I
G1 G2
′
vo 输入信号如下图

 10  V vI/V
VT + =  1 +  DD = 10V
 30  2 15
10
 10  V 5
VT − =  1 −  DD = 5V t
 30  2
vo

输出信号如右图

t

施密特触发器的应用
vI
(1) 波形变 VT
换 V
＋ T-

vI vo
vO

(2) 脉冲整形 Pulse
conditioning
v I

VT
V
＋ T-


(3) Noise immunity

vI

vI


(4) 脉冲鉴幅 Amplitude Checking

vI vO ′
vI

VT
V
＋ T-

vO


8-6 One-Shot 单稳态触发器

• One shot ( mono-stable multi-vibrator)
only has one stable state and one
unstable state.

• When triggered the device changes from
its stable state and remains there for a
fixed period of time, known as the pulse
width, before returning to its stable state.


• The duration time of the unstable state
determined by the circuit parameters, no
related with the triggered pulse.
Trigger
Q tW

• The duration time of the unstable state
determines the pulse width of the output
pulse.


A Simple One-Shot
+V
1
Trigger vI R 0
vI2
0 G1 G2 Q
vO1 1
1
0 C

V
vI tW = RC ln
Basic One-shot−Logic Symbols
V VTH
vO1
_ + = RC ln 2
vI2 ≈R <<R
0.7 RC
VTH on
 −
t

 uC = V (1 − e )
RC
Q
 


• Stable state: Q=0
• Unstable state: Q=1
• The time duration determined by the charge time of
C and R , i.e. the RC time constant.

VDD
tW = RC ln = RC ln 2 ≈ 0.69 RC
VDD − VTH
≈ 0.7 RC


+V
Q
REXT
Trigger C EXT
Q
CX
Q RX / CX
Trigger

Logic Symbol Q

tW = 0.7 Rext Cext

Basic types
of IC one-shot

Nonretrigg Retriggera
erable ble
one-shot one-shot


Non-retriggerable one-shot

• Not respond to any additional trigger pulse
from the time it is triggered until it returns
to stable state.

ignored


74LS121: non-retriggered one-shot

RINT=2KΩ

74121: Schmitt-Trigger Inputs
 This symbol indicates a Schmitt-trigger input. This type of input uses a
special threshold circuit that produces hysteresis, a characteristic that
prevents erratic switching between states when a slow-changing trigger
voltage hovers around the critical input level.


74121: Nonretriggerable One-shot
Schmitt-Trigger Inputs
A1 1
A2 Q
B
VCC RINT RI
CEXT CX
Q
RX/CX
REXT/CEXT

tW ≈ 30ns 内接一个 2kΩ 电
阻 ttW ≈0.7(2KΩ) CEXT
W ≈0.7REXT CEXT
tW=0.7RCEXT ： 30ns to 28s
To achieve a one-shot with a pulse width of approximately 10ms,
using a 74121. If select REXT=20KΩ, calculate the necessary
capacitance ， and show the connection.
th

Retriggerable One-shots

• A retriggerable one-shot can be
triggered before it times out.

retriggered


74122: Retriggerable One-shot

内部是 10kΩ 电阻
tW ≈ 45ns no external resistor and capacitor
 0.7 
tW = 0.32 RC EXT  1 + 
 R 
With external resistor and capacitor

A sequential timing circuit


Exercise:

0.7
tW = 0.32 RC EXT (1 + )
R
0.7
= 0.32 × 47 KΩ × 68µ F × (1 + )
47 KΩ
= 1.0227( s)
≈ 1( s)

The 555 Timer

• The 555 timer is a versatile and widely
used device because it can be configured
in three different modes as a Schmitt
trigger, a one-shot, or an oscillator.

• 555 定时器是一种将模拟电路和数字电
路集成于一体的电子器件。用它可以构
成施密特触发器、单稳态触发器、多谐
振荡器等多种电路。 555 定时器在工业
控制、定时、检测、报警等方面有广泛
96

Comparator

uo
VI+ +
- VO uI+-uI-
VI-

If VI+>VI-, then VO=HIGH
If VI+<VI-, then VO=LOW


555 Timer

555
Threshold
VI(control) Latch

2/3VCC Output
1/3VCC Output
Trigger buffer

Discharge
Discharge
Transisto
r

Reset

Basic operation
UCC
比较结果
5KΩ 2/3UCC
悬空 + V6 V2 R S
Vref 6 R
VA C1
<VA <VB 0 1
5 1/3UCC
5KΩ > VA >VB 1 0
VB + S <VA >VB 0 0
2 C1
> VA <VB 1 1
5KΩ

Vref
VA = Vref , VB =
2

Vcc
Collector
C
If VBE>Vbias, Vc=LOW
Base B
If VBE<Vbias, Vc=HIGH

E
Emitter

100© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

555 定时器的简化功能表：

Q
RD R S Q Q uO T
1 1 0 0 1 0 导通
1 0 1 1 0 1 截止
1 1 1 1 1 0 导通
1 0 0 保持保持保持保持
0 × × 0 1 0 导通

基本 S-R 锁
存器功能表


555 Timer
–one shot?

555
Threshold
VI(control) Latch

2/3VCC Output
1/3VCC Output
Trigger buffer

Discharge
Discharge
Transisto
r

102© 2009 Pearson Education,Reset River, NJ 07458. All Rights Reserved
Upper Saddle

Monostable (One-Shot) Operation


One-shot
R1
555

0.01µF

Trigger

C1


Before Triggering

R1
555

0
1 0
0.01µF
0
Trigger
1

0V on
C1

1

When Triggered

R1
555

0
0.01µF

Trigger

VC1
C1 off
charging

1

At the end of
charging interval
R1
555

0.01µF
0
Trigger
1

2/3VCC VC1
C1
0
discharging
th

Vtrigger

Vc charging discharging
2
VCC
3

Vo

tW


t0 = 0
VCC tW = t1 − t0 = t1
dVC1 (t )
R1C1 + VC1 (t ) = VCC
dt
R1
VC1 (t ) = VC1 (∞) + [VC1 (0) − VC1 (∞)]e −t / R1C1
VC1 (t ) −t / R1C1 VC1 (∞) − VC1 (t )
e =
C1 VC1 (∞) − VC1 (0)
VC1 (∞) − VC1 (0)
t = R1C1 ln
VC1 (∞) − VC1 (t )
v(∞) − v(0) VCC − 0
tW = t1 = R1C1 ln = R1C1 ln = R1C1 ln 3 ≈1.1R C1
1
v(∞) − v(t1 ) VCC − 3 VCC
2


Example
For C1=0.01µF, determine the value of R1 for
a pulse width of 1ms.

−3
tW 1 × 10
R1 = = −6
≈ 91KΩ
1.1C1 1.1 × 0.01 × 10


NE555: Circuit for Monostable Operation


Typical Waveform for Monostable Operation


Astable Operation


R1 555

R2

C1


charging
R1 555
(R1+R2)C1 1

R2 0
1
2
0
Vc1 = VCC
c1
3

C1


R1 555
R2C1 0

R2 1
2
1V 1
Vc1 < CC
Vc1 = VCC
33

+
C1 -
discharging

Vc
2
VCC
3

1
VCC
3

Vo
T

tL
tH


Calculation

t H = 0.7( R1 + R2 )C1 T = 0.7( R1 + 2 R2 )C1
1.44
f=
t L = 0.7 R2C1 ( R1 + 2 R2 )C1

R1 + R2
Duty cycle = × 100%
R1 + 2 R2


R1 555

R2

C1


R1 555

R1C1 R2

C1


R1 555

R2C1 R2

C1


Calculation

t H = 0.7 R1C1 T = 0.7( R1 + R2 )C1
1.44
f=
t L = 0.7 R2C1 ( R1 + R2 )C1

R1
Duty cycle = × 100%
R1 + R2


Exercise

A circuit need a 1Hz clock signal with a
duty cycle of 2/3. R1=40kΩ, C=10µF.
Determine the value of R2.
(1) Using the first connection of 555 timer.
(2) Using the second connection of 555
timer.


NE555: Circuit for Astable Operation


Typical Astable Waveform


Frequency = f(RA, RB, C)


Any Duty Cycle

t H = R1C1 ln 2, t L = R2C1 ln 2, T = ( R1 + R2 )C1 ln 2
R1
D = tH / T = 100%
R1 + R2

uI
2
VCC
3

1
3
VCC 555
0
t
uO
0.01µF
VO
VI
0 t
vI < 1 VCC → vC1 = 1, vC 2 = 0 → Q = 1 → vO = 1
3
1
3 VCC < vI < 2 VCC → vC1 = vC 2 = 1 → Q = 1 → vO = 1
3

vI > 2 VCC → vC1 = 0, vC 2 = 1 → Q = 0 → vO = 0
3


UT+
uI
2 vO 1
3
VCC → VCC ←
ΔUT 3
1
VCC
3

O t
UT-
uO

O 1 2 vI
O VCC VCC
t 3 3
Note: if control voltage VCO (PIN 5) is given,
then
UT+ = VCO UT- = 1/2VCO ΔUT- = 1/2VCO

Voltage Transfer Characteristic

VT − = 1 VCC
3

VT + = 2 VCC
3

VT + − VT − = 1 VCC
3


Homework

• P407
• 6,8,12,18,26,28,30


Summary

• Bistable
– Latch
– Trigger
• One-shot
• 555 Timer
– One-shot
– Astable
– Schmitt-Trigger


Selected Key Terms

Latch A bistable digital circuit used for storing a bit.
Bistable Having two stable states. Latches and flip-flops are
bistable multivibrators.
Clock A triggering input of a flip-flop.

D flip-flop A type of bistable multivibrator in which the
output assumes the state of the D input on the
triggering edge of a clock pulse.

J-K flip-flop A type of flip-flop that can operate in the SET,
RESET, no-change, and toggle modes.


Selected Key Terms

Propagation The interval of time required after an input signal
delay time has been applied for the resulting output signal to
change.
Set-up time The time interval required for the input levels to be
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.


1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above

© 2008 Pearson Education

2. The D flip-flop shown will
Q
a. set on the next clock pulse D

b. reset on the next clock pulse CLK CLK

c. latch on the next clock pulse Q

d. toggle on the next clock pulse


3. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q

c. 3 CLK

Q
d. 4 K

CLR


4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J

c. 3 K
1 2 3 4
d. 4


5. The time interval illustrated is called
a. tPHL 50% point on triggering edge

b. tPLH CLK

c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?


6. The time interval illustrated is called
a. tPHL
b. tPLH D

CLK
c. set-up time
d. hold time ?


7. The application illustrated is a
a. astable multivibrator HIGH HIGH

b. data storage device fout
J QA J QB
c. frequency multiplier fin CLK CLK

d. frequency divider
K K


Output
lines
Q0
8. The application illustrated is a
D

C

a. astable multivibrator R

D Q1
b. data storage device C

R

c. frequency multiplier D Q2

d. frequency divider
C
Parallel data
input lines R

D Q3
Clock C

R
Clear


9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH


10. The circuit illustrated is a +VCC

a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET VCC
DISCH
c. frequency multiplier R2 (6)
THRES OUT
(3)

(2) (5)
d. frequency divider C1
TRIG CONT
GND
(1)


Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10. a


Digitalfundamentals chap7

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