Introduction to stm32-part1
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Introduction to stm32-part1
- 7. CPU, Processor, and SoC Amr Ali Abdel-Naby@2011 Introduction to STM32
- 10. ARM Overview Amr Ali Abdel-Naby@2011 Introduction to STM32
- 11. ARM by Architecture Amr Ali Abdel-Naby@2011 Introduction to STM32
- 12. ARM Application Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 13. ARM Embedded Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 14. ARM Secure/Specialities Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
- 19. CPU Operating Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
- 21. Memory Map Amr Ali Abdel-Naby@2011 Introduction to STM32
- 22. Unaligned Memory Access Amr Ali Abdel-Naby@2011 Introduction to STM32
- 23. Bit Banding Amr Ali Abdel-Naby@2011 Introduction to STM32
- 27. NVIC Exception Entry and Exit Amr Ali Abdel-Naby@2011 Introduction to STM32
- 30. Configure the Exception Vector Table Amr Ali Abdel-Naby@2011 Introduction to STM32
- 33. CoreSight Debug Support Amr Ali Abdel-Naby@2011 Introduction to STM32
- 36. CMSIS Structure Amr Ali Abdel-Naby@2011 Introduction to STM32
Hinweis der Redaktion
- * 07/16/96 * ##
- ISA: Instruction Set Architecture VFP: Vector Floating Point Jazelle: Extension to run Java Byte Code on ARM machines ARM ISA: 32-bit instructions Thumb ISA: 16-bit instructions Thumb-2 ISA: ARM + Thumb TrustZone: Security Extensions SIMD: Single Instruction Multiple Data NEON: Advanced SIMD Virtualization: Hardware Virtualization NVIC: Nested Vector Interrupt Controller WIC:Wakeup Interrupt Controller * 07/16/96 * ##
- They can execute complex operating systems. Phones, notebooks, PDAs, DTVs, set-top boxes… * 07/16/96 * ##
- Suitable for real-time behavior of power-sensitive applications Control systems, automotive, white goods… * 07/16/96 * ##
- SIMs, smart cards, electronic IDs, electronic payments… * 07/16/96 * ##
- N: Negative Z: Zero C: Carry V: Overflow Q: Saturated minimum/maximum result T: Thumb mode ICI: Interrupt continuable instruction To support deterministic interrupt latency for multi-cycle instructions IT: If then To support conditional execution (execute or NOP) T: Thumb mode Always set to 1 ISR #: NVIC is integrated with core * 07/16/96 * ##
- Flat mode: Out of reset mode = Thread mode + Privileged Operations + Main Stack * 07/16/96 * ##
- DMIPS = Dhrystone MIPS, free benchmark to compare CPU perfromance * 07/16/96 * ##
- Aligned access (left, classical ARM) allows efficient access of variables without need of software libraries support but can waste up to 25% of variable space. Unaligned access (right, Cortex ARM) makes more efficient use of memory. Cortex supports both modes by hardware! * 07/16/96 * ##
- Bit manipulation without bit banding (left, classical ARM) needed a read, modify, write operations to change a single bit Bit banding manipulation (right, Cortex ARM) uses alias region to add * 07/16/96 * ##
- * 07/16/96 * ##
- Starts at the bottom of the address range at 0x00000004. Address 0x0000000 is used to store initial SP. The exception vector table stores addresses rather than instructions. The 1 st 15 are for the ones used by the Cortex core itself. * 07/16/96 * ##
- WFI: Wait for interrupt WFE: Wait for event * 07/16/96 * ##
- JTAG (classical ARM) only worked when CPU is halted. HW breakpoints are only two. Real-time trace can be supported using an Embedded Trace Module (ETM) at extra cost. CoreSight (Cortex ARM) can work with old JTAG interfaces! Hardware tracers built-in. Up to 8 HW breakpoints. Can debug in sleep modes. Synchronize CPU with timers when halted. * 07/16/96 * ##
- * 07/16/96 * ##
- CPAL is implemented by ARM to access the CPU HW MWAL defined by ARM but adapted by silicon vendors to access the SoC devices. It is not implemented yet. DPAL similar to CAPL but defined and implemented by silicon vendors. They use CAPL internally. * 07/16/96 * ##