Briefly introduces the features of NETBURST, Core and The Nehalem architecture of INTEL. Along with the Heterogeneous NVIDIA Tegra GPGPU

1. An Architecture Perspective On Modern Microprocessors And GPU - AbhijeetNawal 3/25/2011 1 AN ARCHITECTURE PERSPECTIVE

2. Agenda INTRODUCTION INTEL’S NETBURST ARCHITECTURE INTEL’S CORE ARCHITECTURE INTEL’S NEHALEM ARCHITECTURE SNEAK PEAK AT NVIDIA TEGRA GPU REFERENCES 3/25/2011 2 AN ARCHITECTURE PERSPECTIVE

4. Performance = Frequency x IPC

5. Power = Dynamic Capacitance x Volts x Volts x Frequency.

6. Dynamic Capacitance is the ratio of the electrostatic charge on a conductor to the potential difference between the conductors required to maintain that charge.

7. Higher the No Of Pipeline Stages more Instructions in Pipeline.

8. Higher No Of Pipeline Stages reduces IPC as n/{k+(n-1)} .

9. Low IPC is offset by increasing the clock rate and reducing stage time.

10. Each Instruction is CISC based so decodes into micro operations.3/25/2011 3 AN ARCHITECTURE PERSPECTIVE

12. SSE instructions are 128-bit integer arithmetic and 128-bit SIMD double precision floating-point operations.

13. They reduce the overall number of instructions required to execute a particular program task.

14. They accelerate a broad range of applications, including video, speech and image, photo processing, encryption, financial, engineering and scientific applications.

15. Predecode phase:

16. Before Instruction pipleline fetch and decode phase.

17. Bundles instructions to be parallelly executed.

18. Instructions are appended with bits after fetching from memory as they enter the instruction cache.

19. This unit also has to thus take care of analyzing the structural, control and data hazards. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 4

20. Intel Architectures: Netburst 3/25/2011 5 AN ARCHITECTURE PERSPECTIVE

21. NetBurst Architecture 3/25/2011 6 AN ARCHITECTURE PERSPECTIVE

22. Netburst Microarchitecture 3/25/2011 7 AN ARCHITECTURE PERSPECTIVE

24. A processor appears as two logical processors.

25. Each logical processor has its own set of registers, APIC( Advanced programmable interrupt controller).

26. Increases resource utilization and improve performance.

27. Introduced SSE (Streaming SIMD Extensions)3.0

28. Added some DSP-oriented instructions .

29. And some process (thread) management instructions.3/25/2011 8 AN ARCHITECTURE PERSPECTIVE

31. 20 stage pipeline.

32. Branch Mispredictions can lead to very costly pipeline flushes.

33. Techniques to hide stall penalties are parallel execution, buffering and speculation.

34. Three Major Components:

35. In-Order Issue Front End

36. Out-Of-Order Superscalar Execution Core

37. In-Order Retirement Unit 3/25/2011 AN ARCHITECTURE PERSPECTIVE 9

39. Two major parts:

40. Fetch/Decode Unit

41. Execution Trace Cache

42. Fetch/ Decode Unit:

43. Prefetches IA-32 instructions that are likely to be executed. Details in Prefetching.

44. Fetches instructions that have not already been prefetched.

45. Decodes instructions into µops and builds trace.3/25/2011 AN ARCHITECTURE PERSPECTIVE 10

47. Middle-man between First Decode Stage and Execution Stage

48. Caches the decoded micro operations of repeating instruction sequences avoiding re-decode.

49. Caches the branch targets and delivers µops to execution.

50. Rapid Execution Engine:

51. Arithmetic Logic Units (ALUs) run at twice the processor frequency and thus offset the low IPC factor.

52. Basic integer operations executes in 1/2 processor clock tick.

53. Provides higher throughput and reduced latency of execution.3/25/2011 AN ARCHITECTURE PERSPECTIVE 11

55. Contains multiple execution hardware resources to execute multiple µops parallel.

56. µops contending for a resource are buffered.

57. Meanwhile other µops are executed.

58. Dependency among µops is taken care by appropriate buffering and in ordered retirement logic of retirement unit.

59. Register renaming logic aids to resolving conflicts.

60. Up to three µops may be retired per cycle.3/25/2011 AN ARCHITECTURE PERSPECTIVE 12

62. Dynamically predict the target of a branch instruction based on its linear address using branch target buffer.

63. If none/invalid dynamic prediction is available, statically predicts based on the offset of the target.

64. A backward branch is predicted to be taken, a forward branch is predicted to be not taken.

65. Return addresses are predicted using the 16-entry return address stack.

66. It does not predict far transfers, for example, far calls, interrupt returns and software interrupts.3/25/2011 AN ARCHITECTURE PERSPECTIVE 13

68. Hardware Instruction Fetcher

69. Prefetch Instructions

70. Hardware to fetch data and instructions directly to second level cache.

71. Caching:

72. Supports upto 3 levels of caches.

73. All being exclusive.

74. First Level: Separate data and instruction Cache and trace cache.3/25/2011 AN ARCHITECTURE PERSPECTIVE 14

75. Heading to Core 3/25/2011 15 AN ARCHITECTURE PERSPECTIVE

76. Core Microachitecture 3/25/2011 16 AN ARCHITECTURE PERSPECTIVE

77. Core Microarchitecture 3/25/2011 17 AN ARCHITECTURE PERSPECTIVE

79. Each Core is wider and can fetch, decode and execute 4 instructions at a time.

80. Netburst could however execute only 3.

81. So a quad core processor executes 16 at once.

82. It has added more simple decoder than Netburst.

83. Decoders decoding x86 instructions:

84. Simple: translating to one micro operation.

85. Complex: translating to more than one micro op.3/25/2011 AN ARCHITECTURE PERSPECTIVE 18

87. In previous generation processors, each incoming instruction was individually decoded and executed.

88. Macrofusion enables common instruction pairs (such as a compare followed by a conditional jump) to be combined into a single internal instruction (micro-op) during decoding.

89. Increases the overall IPC and energy efficiency.

90. The architecture uses an enhanced Arithmetic Logic Unit (ALU) to support Macrofusion.3/25/2011 AN ARCHITECTURE PERSPECTIVE 19

91. Wide Dynamic Execution… 3/25/2011 AN ARCHITECTURE PERSPECTIVE 20

93. Core executes one 128 bit SSE in 1 clock cycle.3/25/2011 21 AN ARCHITECTURE PERSPECTIVE

95. Intelligent algorithms for identifying which loads are independent of stores or are okay to load ahead of stores ensuring that no data location dependencies are violated.

96. If at all the load is invalid, then it detects the conflict, reloads the correct data and re-executes the instruction.3/25/2011 AN ARCHITECTURE PERSPECTIVE 22

98. The data only has to be stored in one place that each core can access thereby optimizing cache resources.

99. When one core has minimal cache requirements, other cores can increase their percentage of L2 cache.

100. Load based sharing reduces cache misses and increasing performance.

101. Advantage is higher cache hit rate, reduced bus traffic and lower latency to data. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 23

103. Includes an advanced power gating capability in which an ultra fine-grained logic control turns on individual processor logic subsystems only if and when they are needed.

104. Has many buses and arrays are split so that data required in some modes of operation can be put in a low power state when not needed.

105. Implementing power gating reduced the power footprint to a great extent compared to previous processors.3/25/2011 24 AN ARCHITECTURE PERSPECTIVE

106. Heading to Nehalem 3/25/2011 25 AN ARCHITECTURE PERSPECTIVE

108. Turbo Boost Technology

109. Hyper Threading

110. Smarter Cache

111. IPC Improvements

112. Enhanced Branch Prediction

113. Application Targeted Accelerators and SSE 4.0

114. Intelligent Power Technology

115. Enhanced Virtualization Technology support

118. Connects processors and other components with a new high-speed interconnect.

119. Scalable Architecture in which memory scales with processors.

120. Scalable Shared Memory Implementation Support.

121. Scalable Compute Architecture.

122. Lower Memory Access Latency3/25/2011 AN ARCHITECTURE PERSPECTIVE 28

123. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 29

124. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 30

126. Turbo Boost for a given workload depends on:

127. Number of active cores

128. Estimated current consumption

129. Estimated power consumption

130. Processor temperature 3/25/2011 AN ARCHITECTURE PERSPECTIVE 31

131. Hyper Threading in Nehalem 3/25/2011 AN ARCHITECTURE PERSPECTIVE 32

133. Has 512 entries.

134. Improves the virtual to physical address translation for a page and this in turn further saves memory clock cycles.

135. New three-level cache hierarchy:

136. L1 (32 KB Instruction Cache, 32 KB 8-way Data Cache) per core.

137. L2 caches (256 KB 8-way)per core.

138. L3 cache (8 MB 16-way) is shared among the cores.

139. All caches are inclusive.3/25/2011 AN ARCHITECTURE PERSPECTIVE 33

141. A central queue acts as a crossbar and arbiter between the four cores and the uncore region of Nehalem.

142. Uncore includes the L3 cache, integrated memory controller and QPI links.

144. Improved implementation of instructions enforcing synchronization like XCHG so that existing threaded software will see a performance boost.

145. Improved Hardware Prefetch and Better Load-Store Scheduling. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 35

147. First identifies repeating instruction sequences.

148. Once identified the traditional branch prediction, fetch and decode phases of execution are temporarily turned off while the loop executes.

149. This saves the cycles that might have been otherwise wasted in these pipeline stages due to repeated set of instructions. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 36

151. New Second-Level Branch Target Buffer: To improve branch predictions in large coded apps (e.g., database applications).

152. New Renamed Return Stack Buffer: Stores forward and return pointers associated with calls and returns.

153. SSE 4.2:

154. Introduces seven new SSE 4.2 instructions including four that optimizes string and text processing.

155. STTNI (String and text new instructions):

156. Operate on 16 bytes at a time.

157. This boosts the XML parsing speed and enables faster search and pattern matching, lexing, tokenizing and regular expression evaluation.3/25/2011 AN ARCHITECTURE PERSPECTIVE 37

158. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 38

160. Allows independent individual idling of a core to non zero power reducing idle power.

161. Automated Low-Power States:

162. Automatically put processor and memory into the lowest available power states that will meet the requirement of the current workload. 3/25/2011 AN ARCHITECTURE PERSPECTIVE 39

164. So hypervisor can pin Virtual machine to a specific execution microprocessor and its dedicated memory.

165. Hardware-assisted page-table management:

166. Allows the guest OS more direct access to the hardware and reducing compute intensive software translation from the hypervisor.

167. Directed I/O:

168. Speed data movement and eliminates much of the performance overhead by giving designated virtual machines their own dedicated I/O devices, thus reducing the overhead of the VMM in managing I/O traffic.

169. Virtualized Connectivity:

170. Integrating extensive hardware assists into the I/O devices

171. Performing routing functions to and from virtual machines in dedicated network silicon, it speeds delivery and reduces the load on the VMM and Server Processors.

172. Improves two times the throughput than non-hardware assisted devices.3/25/2011 AN ARCHITECTURE PERSPECTIVE 40

174. Branch Prediction: advanced RSB and L2 Branch Predictor.

175. Unified 2nd Level TLB: 512 entry L2 TLB against 256 entry of core.

176. Macrofusion: Condenses 64-bit Macro-ops than 32-bits in Core.

177. The Loop Stream Detection: More efficient in Nehalem.

178. The Execution Engine and the Out of Order executor:

179. The Reorder Buffer has been made a third larger- up from 96 to 128 Entries.

180. The Reservation Station (which schedules operations to available Execution Units) has been given an extra four slots allowing 36 Entries .3/25/2011 AN ARCHITECTURE PERSPECTIVE 41

181. SNEAK PEAK ATNVIDIA TEGRA GPU 3/25/2011 42 AN ARCHITECTURE PERSPECTIVE

184. Rendering 3D Visuals, Gaming and Touch Interface

185. Video Decode Processor

186. Macroblock Algorithms, VLD and Color Space Conversions for HD video Streaming and Playback

187. Video Encode Processor

188. Video Encode Algorithms for HD Streaming Recording3/25/2011 AN ARCHITECTURE PERSPECTIVE 44

190. Light Balance, Edge Enhancement, And Noise Reduction for Real Time Photo Enhancements

191. Audio Processor

192. Analog Signal Audio Processing

193. Dual-Core ARM Cortex A9 CPU

194. For General-Purpose Computing eg. Web Surfing

195. ARM7 Processor

196. System Management Functions like monitoring Battery, Turning on/ off Processing Units.3/25/2011 AN ARCHITECTURE PERSPECTIVE 45

198. Intelligent to Achieve Lowest Power Footprint.

199. Multi tasking Loads handled by enabling dedicated set of Processors.

200. For Non Multi tasking Loads only the processor most optimized for it is turned on and rest are powered off.3/25/2011 AN ARCHITECTURE PERSPECTIVE 46

202. NvidiaTegra White Paper

203. http://www.bit-tech.net

204. http://www.trustedreviews.com/cpu-memory/review/2008/11/03/Intel-Core-i7-Nehalem-Architecture-Overview

205. http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu 2041-3.html

206. www.wikipedia.com3/25/2011 AN ARCHITECTURE PERSPECTIVE 47