2. Analog to digital converter (ADC) circuit
1- What is the Analog and digital signal?
2- What is the ADC?
3- Type s of ADC
3. Objective of this experiment:
To understand the concept and the principle of analog to digital conversions
4. Analog and digital signals
Analog signals are continuous in value and in -
time
Digital signals are discrete in value and in time -
5. Digital-to-Analog Conversion
In order to control analog outputs, digital outputs must first be converted to
analog form using a digital-to-analog converter (also referred to as a DAC or
D/A converter).
digital Analog
D/A Converter Output
Analog Output from digital
(Digital Input to D/A Converter)
Analog-to-Digital Conversion
In order to read analog inputs, the analog inputs must first be converted to digital
form using a an analog-to-digital converter (also referred to as a ADC or A/D
converter).
Analog A/D Converter DIGITAL
Input
Digital Output from A/D Converter
6. -How we Convert analog signal into digital signal?
we used ADC which is opposite of DAC in last experiment device for
converting analogue signals into digital signals or circuit that has single input
and multibit binary outputs
The number of output bits will determine the ADC resolution the number of
output bit is from 4 to 20 bit ADC with higher number of output bit will have
higher resolution
7. To convert analog signal into digital signal using ADC the signal through three stage
:
1- sampling
2-quantizing
11. This circuit is contain DAC,COUNTER,COMPERATOR
1-Vin : applied input analog signal is one input of comparator
2-Vout : is the output of DAC which is the second input of comparator
3- count(control line):if it is low the counter turn on and stop the
counter if it high
4- output of comparator is connected to (count)and end puls
5-start pulls connect to /clr that is initiate the counter (reset) it
determine to start convert analog signal into digital value
input signal
6-clock (increment the counter)
test signal
7-D0-DN output that is digital value
DAC
b7 b0
counter
12. Operation:
1- analog signal input is applied on (vin)of the comparator
2-start pulse is applied to counter and reset the 8-bit binary counter so it begin
count from “0”
3- counter generate signal from (b0-b7) which is input of DAC that convert it
into analog signal with vout
4- if the voltage of input signal is higher than voltage on test signal (output of
DAC) then the output of the comparator is high so the clock will increment the
counter
5- if the voltage of input signal is less than voltage on test signal (output of
DAC) then the output of the comparator is low so the enable the end pulse to
stop the conversion of analog signal
input signal
test signal
DAC
b b0
7 counter
13. -To find the maximum conversion time can be calculated as :
2^n-1*clock period ( for example 8-bit counter with 100khz)
so the max=1.28ms (n=number of bit in the counter)
-advantages :
It has simple structure
-disadvantages :
Very slow require 2^n-1 clock cycle to convert each sample
14. 2- Dual slope ADC:
It convert an unknown analog input to time interval that can be measured by
counter
It consists of integrator,comparator,control circuit ,BCD countar with 7-segment
lCD,lED
15. Operation:
1- when the analog input is applied on (vin )
2- the control circuit will reset the counter and connect the analog input to
input of the integrator
3- the integrator capacitor will start charging by integrating the analog input
for afixed time period (t1) at the end of t1 output of the integrator is a function
of the analog input and the input of the integrator is switched to arefrence
voltage (vref)
4- at this point the integrator capacitor will start discharching and the counter
start counting the discharge time t2 until the capacitor is completely
discharged
5- when t2 is reached the comparator change its logic state and the counter
stop counting the output of the counter is proportional to analog input
6- when the capacitor is charging vout has negative slope ,when discharging
vref ,vin, vout have positive slope
16. *T1,the vout=vin/rc*t1
So the vout have negative slope (charging time)
*T2,the vout =vref*t2/rc
So the vout have positive slope
SO the unknown input voltage is expressed as t2/t1 vref
17. Advantages of dual slope ADC :
1- high accuracy
2- inherent noise immunity
18. Flash Comparator converter
YOU can observe from the
circuit that
It consists from comparators and
special type of encoder called
priority encoder
19.
20. OBSERVATION ON CIRCUIT
There are 7 ranges for each comparator starting
from v/8,2v/8,........,v.
Triggering comparator by voltage large than V/8
Binary output can be obtained if output of
parallel comparators encoded using priority
encoder.
Now...................what is priority
encoder?
21. Priority encoder :encoder circuit that includes
priority function .
It used when we have more than two outputs active
"high (1)” at the same time so output will be input
that has highest priority.
Example suppose we have 4-inputs ,D0 has
lowest priority and D1 has highest priority
So truth table will be
D0 D1 D2 D3 X Y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
23. Example:
Suppose that 5V/8<Vin<6V/8 so W1~W5 are
equal to one & W6,W7 are 0 “1111100” binary
output is Y2Y1Y0=101
*Features:
Fastest but most expensive
This type has fast conversion rate so number of
shortcoming less
Keep in mind ......if resolution improved this
mean increase number of comparators and as
result increase cost tremendously.
24. SUCCESSIVE APPROXIMATION
This type of ADC is improvement result from
Counter ramp DADC.
Observe that :
It consists of DAC and comparator
Counter replaced by special circuit SAR
‘*successive Approximation Converter *
MSB cause DAC output to be half input reference
voltage.
Next........................successive Circuit
25.
26. OPERATING CYCLE
Conversion
intiated:SAR=0but
immediately MSB=1 but
other bits lower still 0
Control circuit Comparator
generate final compare DAC
output and send to output with anlog
Buffer circuit input Vin
Final binary output If Vout>Vin so MSB=0
found so this mean and we go to the next
“End of Conversion “ MSB=1
Vout compared with If Vin>VoutMSB=1
Vin and it will set or
reset continuously. And next MSB=1
27. Operating
speed for successive
converter
Operating speed Number of Clock
period
bits
*This type of converter has
high speed operating cycle .
*Most application use this
type because of its high speed.
30. WR control input when CS=0 and conversion start .
WR=0,Counter reset conversion start .when
WR back to “1”.
INT pin signals the end of conversion
It is =0 when conversion start and returns to 0when conversion
ends.
Vin(+),Vin(-) analogy signal inputs[negative and positive
voltage]
CLK IN clock input .
31. MORE ABOUT........................ CK
Clock frequency of converter
Limited (100KHz-1460KHz]
If CK frequency exceeds 1460KHz frequency
divider used to reduce it.
Now how ADC generate its own clock signals?
Adding RC circuit between CLKIN ,CLK R .
Frequency=1/(1.1 *R*C)
32. ( Impedance R range (10-50K
• Pin 9 manipulate to get different input voltage ranges.this mean we can control
input voltage with out affected by supplied voltage.
GND two types:
*A GND for analog ground.
*D GND for digital ground.
Largest analog input into the ADC0804 is the fullscale
When input=Vref ,output FFh
When pin 11 open Vref=Vcc
33. Input
impedance
"resistor Resolution
+capacitors”
Accuracy: Conversion
degree of Time: time
non- required to
linearity convert
and
interference
ADC specification analog input
voltage to
.[quantizing digital
error] and Error output .
resources
OUT put stability:ADC
code :in sensitivity to
binary or temperature
BCD change.
Analog input
voltage
35. Synthesis of system level bus interfaces
1- introduction
2- problem formulation
3- bus generation algorithm
36. Introduction :
In this paper the outhers implement single bus from set of communication channels
And we present a bus generation algorithm which determines the width of bus
Implemented and tradeoffs between the width of the bus and performance of the
processes communicating over the bus this algorithm give the system level constraints
such as data Transfer rate ,number of pins and allow several channels that may be
transfer different sizes Of data to be implemented as single bus
37. *How we partitioning system level :
* A system can be viewed as set of processes which communicate with
each other over communication channels
*System level partitioning in two groups:
1- groups processes and variables in the system specification into
modules(representing chips and memories)
2- groups the channels to be implemented by buses
*Interface synthesis:
Set of task performed to implement communication between modules in a
system
38. Module 1 Process A
Process A Variable IR,PC,ACCUM
Variable Procedure receive(…)
IR,PC,ACCUM …..
Procedure send(…)
IR<=MEM(PC)
STATUS<=X”0A” …..
MEM(AR)<=ACCUM Receive(busb ,PC ,IR)
Bus generation ……
Bus b Send(busb,”0A”)
…….
ch1 Ch3 Send(busb ,AR
ch2
,ACCUM)
Process A1 Process A2 BUS B Module 2
Variable Variable 8 bit
MEM:intarray STATUS Process A2
Process A1
Variable STATUS
Variable
Procedure receive(…)
MEM:intarray
……….
Procedure send(….)
Procedure receive(…)
Loop
Variables processes >modules Receive(busb,STATUS)
Send(busb ,MEM)
…… END LOOP
Channels>buses Receive(bus, MEM)
39. Figure 1 :
- process A after system partitioning is mapped to two system modules
-The variables MEM and STATUS mapped to processes A1 and A2 in
different module
-Process A processes reads and writes data to the variable MEM over
channels ch1 and ch2
-STATUS is accessed over channel ch3
-ch1,ch2,ch3 have been grouped into bus b
-Bus generation is the interface synthesis task that determines the bus
structure (number of data and control lines) for implementing group of
communication channels
-It determines the buswidth bus generation directly affects two critical
design metrics:
-Performance of the processes comunicating over bus
-Interconnect cost of the modules measure number of wire and pin of
modules
40. After system partitioning we wish to synthesize a bus to
implement communication between different processes
communicating over channel each channel may
transfer data of different sizes
Firstly we explain the problem formulation of bus
generation and then we explain the algorithm
which determine the bus width finaly we take
about experiments with bus generation
41. 1- computing bus and channel rates:
Bus rate :
Maximum rate at which data can be
transferred across the bus
To find the bus rate assume that
-width(B) is the number of data line in bus b
-delay (B) total delay used by process to transfer data over the
bus
So
Bus rate(B)=Width(B)/Delay(B)
42. To find the total execution time for any process consists of two components:
1- computation time (comptime(p)) : average start to finish execution time
required by process to perform all its internal computations (these computations
represent any statement in the process loop, conditional statements)
2- communication time (commtime(p)): time spent by the process accessing data
external to process (variables which are in another process/module as result of
system partitioning)
commTime(p)=Access(p , c)*(bits(C)/Width(b))*Delay(B)
Where Access(p , c) represent the number of times process (p) will
transfer data over channel (c) ,bit(c ) is inferred from the type of
variable being accessed over channel c
43. Channel average rate is defined as the rate at which data is sent over channel c
over the lifetime of process communicating over rate
Channel average rate (AveRate)=access(p , c)*Bits(c)
/compTime(p)+commTime(p)
Channel peak Rate: rate at which single data transfer over channel
44. Average data transfer
8 8 rate
Channel A A1 A2 (2*8bits)/4s=4b/s
16
16 16
Channel B B1 B3 (3*16bits)/4s=12b/s
B2
8 16 16 16
Bus AB A1
B1 B2 A2 B3 (4+12)=16 b/s
t=0s t=1s t=2s t=3s t=4s
Channel A sends 8 bits of data twice over the 4s ,channel B sends 16 bit of data
(3)over the 4s,bus AB send different size of data 8BIT AND 16 BIT over 4s
The peak rate of a is 8bit/s ,and of b is 16 bit/s
45. 2- relating bus and channel rates:
1-bus is more efficient implementation because it never idle and has
100%utilization
2-consider two channels A and B assume that the 4s time interval shown of
data transfer over the life times of process communicate over channels A
and B
3- channels A and B have average rates 4 and 12bit/s
4- if channels A and B are implemented as single bus AB then the bus AB
need to send data at the rate of 16bit/second to be able to satisfy the data
transfer of two channel A and B
5- bus AB we attempt to utilize the idle time slots of one channel for data
transfer of other channels by synthesizing a bus over which data transfer at
constant time
46. 3- Constraints for bus generation:
For implementation the designer can specify constraints such as:
1- Bus Width : Maximum/minimum bus width (pins, modules)
2- channel Average rate (minimum channel and maximum channel )(constraints for
process communicating over the channel
3-channel peak rate: to ensure that transfer of single data item over the bus don’t
take long time
47. determine bus width to
implement group of channels.
For each one time only one channel can
The data and control bus are disjoint.
transfer data.
48. Observation:
1.If bus width is greater than address
and data bit width so data and address
bits are sent simultaneously over the
bus if opposite they sent separately.
Note:
*In last case address must be latched in
the receiving process.
*If bus width smaller than data bits so
data sent on multiple interfaces.
How we use this bus?
₩ .Variables mapped to another module .
₩. These mapped variables modeled by separate process.
₩. Separate process send/receive variable values over channel
in response to requests from process.
49. By using this algorithm we have to extract two cases :
*Feasible implementation.
*No constraints case .”Bus width corresponds to 1 to serial
data transfer”
Feasible implementation
Each bus width have bus rate &channel average rate must
be calculated.
bus rate greater than sum of channel average rate as below
Bus Rate=AveRate(channel)
CEB
Select one that has least cost.
50. Min BW&MaxBW
range of bus
width.
MinCost
represent
AveRateSum:sum min.cost
of the channel computed for
average rates for all feasible
specific value of implementatio
variables n of the bus.
CurrBW
CurrBW:curr MinCostBWRe
ent bus width present
evaluated by buswidth for
algorithm. min.cost
51.
52. Bus algorithm show 5 steps:
1.Determine the buswidth to be examined .
MinBW=1,MaxBW=max(Bits(channel))
2.Compute bus rate corresponding to CurrBW.
BusRate(B)=CurrBW/Delay(B)
3.Deteminethe channel average rates.
53. Now if BusRate>sum of average rates of all channels
then we have a feasible implementation for the bus
.so....go to next step.else go to step 2
4.Determine cost for CurrBW.
Cost of bus=(squares of violations of each constraints
[weighted by relative weights specified for them])
5.Select the buswidth.
To determine the least cost from many feasible
implementation solutions.
54. Note :
Problem.......
If there is more than one channel in the implementation
these would progressively delay the process
communicating over bus this situation when we have
more channels have own very high average rate
requirements are grouped to gather to have single bus
So ........solution is split the group of channels to be
implemented by more than one bus and use feasible
implementation.
55. EVAL-R3 &CONV-R2 Processes of FLC access array variables trRu0
& trRu2 over communication channels ch1 & ch2 that merged to
be implemented as a single bus.
All execution times data transfer rates are expressed in terms of
clocks
56. Both channels access array variables which have 128
words (7 address bits)of 16 bits each.
MinBW=1 and MaxBW=23
CurrBW=18.
For handshake rotocol,delay(b)=2 clocks
[BusRate(B)=18/( 2)=9 bits/clock.]
AveRate(ch1)=(128*23)/(515+(128*[28/18]*2)]
=2.86 bits/clock
AveRate(ch2)=(128*23)/[129+(128*[23/18]*2)
=4.59 bits/clock
57. BusRate(B)>AveRate(ch1)+AveRate(ch2) we have
fessible solution for CurrBW=18.
Cost =peakRateCost(ch2)^2=(10*(10-9))^2=100
If repeating the algorithm on other range for
buswidth from[1-23].
For graph:
1.This is the buswidth that is selected for implementing
the bus consisting of channels ch1 and ch2.
2.We note that the minimum value of the cost function
is [0] which occurs at a buswidth of 20
58.
59. Bus generation
algorithm
implemented by
SpecSyn system –level
partitioner .
Usage of bus generation algorithm for
protocol generation
*For selected buswidth VHDL receive/send
procedures defining the data transfer over bus are
generated for each channel
*Accesses to variables in the processes are replaced by
the appropriate send/receive procedure call .
60. Application of bus generation algorithm
Ethernet network processor.
Bladder volume controller.
Fuzzy logic controller.
Now let is disscus fuzzy
logic controller
61. *FLC consists of two inputs
*FLC sense the temperature and humidity in a room
and evaluate four rules to control the operation of
an air conditioning system .
*system partitioning mapped processes & array variables
that store FLC membership functions & fuzzy logic
rules to different modules then creating several
channels between modules .
62.
63. 1.Each bus width has protocol required for all channels
in the bus.
Performance estimator used to get execution time of
processes.
BW Execution
Example”
time
Process (CONV-R2)has max execution time constraints
of 2000 clocks so only bus width over 4 bits needed to
implement bus .[back to figure 6]
64. This by specify suitable constraints and weighting
we implement bus generation algorithm to 3 sets of
constraints. [3 designs]
65. Design A
Min peak rate ch2 =10 bit/clock.
Feasible bus implementations are those which have
bus rate >sum of individual channel average rates
Min cost function for bus width of 20 bits.
Design B
Min & max Bus width constraints with relative weight
half peak rate constraint for ch2 specified.
Min cost function occurs at bus width of 18
66. Design C
This design for implement both channel A & B using
16 bit bus.
Both min & max bus width constraints specified to be
16 bits & very high relatively weights.
It has least cost function of all feasible
implementations.
