SPICE MODEL of S-89110A in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.

1. Device Modeling Report
COMPONENTS: OPERATIONAL AMPLIFIER
PART NUMBER: S-89110A
MANUFACTURER: SEIKO INSTRUMENT
REMARK TYPE: (CMOS OPAMP)
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

2. Spice Model
U1
IN+ VDD
VSS
-
+
IN- OUT
S_89110A
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

3. MOSFET MODEL
Pspice model
Model description
parameter
LEVEL
L Channel Length
W Channel Width
KP Transconductance
RS Source Ohmic Resistance
RD Ohmic Drain Resistance
VTO Zero-bias Threshold Voltage
RDS Drain-Source Shunt Resistance
TOX Gate Oxide Thickness
CGSO Zero-bias Gate-Source Capacitance
CGDO Zero-bias Gate-Drain Capacitance
CBD Zero-bias Bulk-Drain Junction Capacitance
MJ Bulk Junction Grading Coefficient
PB Bulk Junction Potential
FC Bulk Junction Forward-bias Capacitance Coefficient
RG Gate Ohmic Resistance
IS Bulk Junction Saturation Current
N Bulk Junction Emission Coefficient
RB Bulk Series Resistance
PHI Surface Inversion Potential
GAMMA Body-effect Parameter
DELTA Width effect on Threshold Voltage
ETA Static Feedback on Threshold Voltage
THETA Modility Modulation
KAPPA Saturation Field Factor
VMAX Maximum Drift Velocity of Carriers
XJ Metallurgical Junction Depth
UO Surface Mobility
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

4. Output Voltage Swing
Evaluation Circuit
U3 U4
IN+ VDD IN+ VDD
VSS VSS
-
+
-
+
IN- OUT IN- OUT
VOH VOL
V3 V4
V5 R2
S_89110A 3 S_89110A
V1 V2 R3 1
2 1 2 1MEG
1MEG
V6
3
0 0
Simulation result
VOH
VOL
Compasion Table
Measurement Simulation %Error
VOH (V) 2.9 2.9003 -0.010
VOL (V) 0.1 0.098494 1.506
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

5. Input Current
Evaluation Circuit
U1
IN+ VDD
VSS
-
+
IN- OUT
OUT
V1 V2 S_89110A
0Vdc
V3
0Vdc 3
0
Simulation result
Simulation
Compasion Table
Measurement Simulation % Error
Ib (pA) 1 1 0
IOS (pA) 1 1 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

6. Input Offset Voltage
Evaluation Circuit
U2
IN+ VDD
VSS
-
+
IN- OUT
OUT
V1
S_89110A
0 3 V2
0
Simulation result
Simulation
Compasion Table
Measurement Simulation %Error
VOS (mV) 3 2.9876 0.413
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

7. Open loop Voltage Gain
Evaluation Circuit
U2
IN+ VDD
VSS
-
+
IN
IN- OUT
OUT
V3
3
V1 S_89110A
VOFF = 0
VAMPL = 0
FREQ = 0
AC = 1m
DC = -2.9876m
0
Simulation result
Simulation
Compasion Table
Measurement Simulation %Error
Av (dB) 80 79.609 0.489
fT (kHz) 175 166.510 4.851
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

8. Common-Mode Rejection Ratio
Evaluation Circuit
R4 R7
500k 500k
U1 U2
VIN1 R2 VIN2 R6
IN+ VDD IN+ VDD
V2 V4
1k 3 1k 3
VSS VSS
-
+
-
+
R1 0 R5 0
0 IN- OUT 0 IN- OUT
out1 out2
1k 1k
R3 R8
S_89110A S_89110A
VIN1 500k VIN2 500k
2.3 1.5
1.5 V1 1.5 V3
0 0 0 0
Simulation result
Simulation
 VIN1  VIN2 RF  RS 

CMRR = 20log   
 V OUT1VOUT 2 RS  
Compasion Table
Measurement Simulation %Error
CMRR (dB) 70 71.625 -2.321
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

9. Slew Rate
Evaluation Circuit
U2
IN+ VDD
VSS
-
+
IN- OUT
OUT
V1 = 0 V1
V2 = 5
TD = 50u V2
TR = 0 S_89110A
TF = 0 R1 C1
PW = 500u
PER = 1m 1MEG 15p 3
0
Simulation result
Simulation
Slew Rate = Slope of output
= (2.6295-378.486m)/(114.774u-82.67u)
= 0.0701 V/us
Compasion Table
Measurement Simulation % Error
SR (V/us) 0.07 0.0701 -0.143
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005