1. Chapter 10
Characterization and Specification
Abstract The specification of the converter is a dominant mechanism to align
the wishes of the user to the possibilities of the designer. Directly coupled to the
specification is the measurement technique that serves to establish a numerical
value for a theoretical concept. This chapter discusses the fundamentals of the
characterization and measurement techniques, such as histogram testing.
Every system designer of analog-to-digital conversion techniques will use the spec-
ified parameters to determine the usefulness of a converter for the application. The
definition of parameters is mostly well described; however, the actual measurement
of the parameter can still leave margins for variation [107, 294, 295]. A supplier
may restrict himself to the typical value of a parameter; however, also the maximum
and minimum values can be part of a specification. Moreover, it may be useful to
examine the temperature and supply voltage ranges in which the specified value for
a parameter is guaranteed.
The application will determine which parameters of a converter are most relevant.
For high-quality audio equipment the distortion is relevant. In communication
equipment intermodulation is important as well as the spurious-free dynamic
range in a certain frequency span. Next to the standard specification points of
analog-to-digital converters that are listed in Table 10.1 also a range of secondary
qualifications can be taken into account. Examples are: phase behavior, package
(height, volume, pin), tolerance to light (e.g., in an optical sensor), available
references (internal or external), and input impedance. The correct application of
a converter depends crucially on a good characterization, test setup, and parameter
extraction.
M.J.M. Pelgrom, Analog-to-Digital Conversion, DOI 10.1007/978-1-4614-1371-4 10, 469
© Springer Science+Business Media, LLC 2013

2. 470 10 Characterization and Specification
Table 10.1 Main Specification Symbol Unit
characterization parameters
of an analog-to-digital Nominal amplitude resolution N 1
converter Sample frequency fs Hz, s−1
Bandwidth BW Hz
Integral linearity INL LSB
Differential linearity DNL LSB
Monotonicity
Missing codes
Harmonic distortion THD dB
Intermodulation distortion IM2,3 dB
Spurious-free dynamic range SFDR dB
Signal-noise and distortion ratio SINAD dB
Signal-noise ratio SNR dB
Effective number of bits ENOB 1
Dynamic range DR dB
Jitter σt ps
Power consumption P W
Temperature range T ◦C
Power supply VDD V
10.1 Test Hardware
A correct evaluation of a converter starts at the beginning of the chip design.
Interfaces to and from the test equipment must be defined. These analog or digital
drivers and buffers should not interfere with the test or jeopardize the signal quality.
High sampling frequencies require low-jitter buffers and high-frequency analog
output signals require wide bandwidth buffers. Every experiment starts with a PCB
on which the device under test (DUT) is mounted. Some more points must be
considered when designing a test board:
• Analog and digital power supplies and signal sources should be kept separate and
only connected together on one single node. Be aware of coupling of earth loops
via the mains plug.
• Provide sufficient decoupling: microfarad electrolytic capacitors for the low
frequencies and metal or ceramic capacitors for the high frequencies. Mount them
as close to the package as possible.
• In the evaluation phase it may be tempting to use a tool that allows to exchange
the samples easily. However, these tools add a lot of distance between the die
and the PCB and therefore add many nanohenries of inductance. In Fig. 10.2
a technique is shown where the surface-mounted device is pushed onto the
connection electrodes of the printed-circuit card. This setup keeps the distances
short.
• High-frequency connections must be laid out keeping in mind that every wire
is a transmission line. PCB lay-out packages have options to design wires and
surrounding grounding in such a way that a defined impedance is achieved.

3. 10.1 Test Hardware 471
Fig. 10.1 Test set-up for digital-to-analog conversion
• Every signal must be properly terminated close to the test device. This certainly
holds for digital signals. Non-terminated digital signals will ring and inject
spurious charges into the substrate.
A professional measurement setup for characterizing an analog-digital converter
uses a computer to control the setup and to analyze the measurement results; see
also the relevant IEEE standardization documents [106–108]. Many professional
evaluation set-ups are constructed with racks of measurement equipment connected
by some interface bus. A computer equipped with test software will control the
equipment, setup voltages and currents, step through the signal range, and capture
the data in a data logger of several gigabytes storage. The signal source and the
generator for the sample rate have to comply to more stringent specifications than
the DUT. Modern signal sources are equipped with an extensive user interface,
which goes sometimes at the cost of signal distortion and purity. Old “analog”
generators are often to be preferred over the modern equipment of the same price
level. A well-known method to obtain a high-quality measurement signal uses
passive filters, such as the anti-alias filter in Fig. 10.1. This setup avoids that
remaining distortion components, noise of various origins as well as cross talk of
the generators internal processing, disturb the measurement. The analog-to-digital
converter is normally mounted on a load board: a printed-circuit board adapted for
connection to the main test equipment; see Fig. 10.2. As a direct coupling of the
converter to the test equipment may result in long wires, loading, and ground loops,
the (digital) side of the converter is buffered near the device. This buffer will act as
a decoupling of signal ringing over the long connection lines. The buffer shields
the converter from the high energies that are associated with driving the tester.
In extreme cases the connection between the tester and the device is made via an
optical fiber, so that a perfect electrical separation between the converter and the
tester is achieved. In the tester a data storage device (data logger or data grabber)
will store the high-speed data that comes from the converter. The computer can

4. 472 10 Characterization and Specification
Fig. 10.2 Test board for measuring an analog-to-digital converter (courtesy: R. v. Veldhoven)
Fig. 10.3 Measurement setup for a digital-to-analog converter
then in a second phase analyze the data at a convenient speed. The postprocessing
results in an output as shown in Fig. 10.6. An important part of the requirements for
analog-to-digital testing holds similarly for digital-to-analog converters. Figure 10.3
shows a potential setup for the test. In accordance with the principle of coherent
testing of the next section, the computer generates and stores a number of data
samples in the storage. A cyclic process reads the data at the desired sample rate and
feeds the digital-to-analog converter. The required measurement equipment must
exceed the specifications of the to-be-tested device. By applying a passive filter, the
main component of the output signal can be suppressed so that the measurement

5. 10.2 Measurement Methods 473
Fig. 10.4 The first track-and-hold circuit is tested at high input and high sample rate. The second
device runs a sample rate that is an integer factor slower. The resulting output signal contains
signals that correspond to the first track-and-hold output signal and all harmonics
equipment only needs to have sufficient resolution for the remaining components.
The signal analysis will involve a spectrum analyzer or another form of analog-to-
digital conversion.
Example 10.1. How can a high-speed track-and-hold circuit be tested without
having to accurately measure high-frequency output signals?
Solution. Subsampling can be used to test a sampling device such as a track-and-
hold circuit. Two devices are cascaded as in Fig. 10.4. The first device is operated
at a high sample and signal rate. The second track-and-hold circuit samples the
output of the first device at an integer fraction of the sample rate. The original output
signal of the first track-and-hold circuit and its harmonics are subsampled to a low
output frequency that can be easily measured. The “subsample” method requires
quite some skills to interpret correctly the resulting frequency components.
10.2 Measurement Methods
10.2.1 INL and DNL
A simple way to evaluate the behavior of a converter is to apply a sawtooth signal to
the input. For converters with specifications on absolute accuracy a programmable
voltage source is a good choice. Less demanding applications can start with a
generator or a self-built circuit. If the sawtooth is sufficiently slow, there will
be enough sample moments to determine the DC parameters as INL, DNL, and
monotonicity. If these parameters need to be established at a 0.1 LSB accuracy level,
a data storage of 10 × 2N samples is necessary.
A sawtooth signal is not the most critical signal for fast converters and is not easy
to generate at high precision. Nyquist analog-to-digital converters with maximum
input frequencies ranging from tens of Megahertz into the Gigahertz range require
the use of statistical methods. The input signal for measuring dynamic specifications
is then preferably a sine wave. This test signal can be obtained with a relatively

6. 474 10 Characterization and Specification
Fig. 10.5 The ideal distribution of hits when a full-scale sine wave is applied to a 5-bit analog-to-
digital converter
high quality through the use of passive filters. These fast and relatively accurate
methods for determining INL and DNL use the statistical properties of sine waves.
When a full-amplitude sine wave with period Tsw is applied to a converter, there is
a probability for every code to be hit a number of times. A sine wave will hit more
levels in the upper and lower range than in the middle. If the conversion range is
defined mathematically between 0 and 1, a full-amplitude sine wave takes the form
y(t) = 0.5 − 0.5 cos(2π t/Tsw ). (10.1)
The signal will go from the lowest level to the highest level in half of a cosine
period. Δy is a fraction of the range (e.g., 1 LSB) at conversion level y and is called
a “data bin.” Δty is the corresponding fraction of time of the half cosine wave. Δty
corresponds to the hits in bin Δy: while half of the cosine period (Tsw /2) corresponds
to the total amount of samples. The ratio Δty /(Tsw /2) is now the fraction of hits that
end up in bin Δy.
1
t= arccos(1 − 2y)
ωsw
dt 1
=
dy ωsw y − y2
Δty 2 dt Δy
= Δy = (10.2)
Tsw /2 Tsw dy π y − y2
Δy is chosen as 1 LSB. Figure 10.5 shows a characteristic distribution of the number
of hits per level or binning of levels. A test run generates the actual measured
distribution of the converted values of a sine wave. This measured distribution is
compared to this theoretical curve, and the deviations (scaled to the same level)
result in an INL and DNL plot, as is shown in Fig. 10.6.

7. 10.2 Measurement Methods 475
Fig. 10.6 Output of an automated test set-up. Top: histogram output, middle: DNL, bottom: INL
This “histogram” method can be used at any frequency. It provides also informa-
tion on the linearity problems at higher signal frequencies. The DNL measurement
is not optimum as non-monotonicity in this measurement method is not found. Non-
monotonicity just changes the DNL value of the corresponding code; the associated
step back is missed. An additional sawtooth test is required. The calculation above
suggests that the input amplitude of the sine wave must accurately match the analog-
to-digital converter range. In advanced test packages, routines exist that will allow
also amplitudes that extend over the input range. A reconstruction of the input is
also possible; see Fig. 10.7.
Example 10.2. How many samples must be acquired to specify the accuracy of the
INL with 0.1 LSB?
Solution. In the case of an ideal sawtooth the number of samples in a bin with a
size of 1 LSB is determined by the slope of the sawtooth. If the sawtooth rises from

8. 476 10 Characterization and Specification
Fig. 10.7 Reconstructed wave form of a 311 MHz signal sampled at 1.44 Gs/s [184]
minimum reference to maximum reference in NST sample periods, then the average
number of hits per bin will be NST /2N . In order to obtain an accuracy of 0.1 LSB,
NST must exceed 10 × 2N . The above calculation for the histogram method allows
to determine the minimum number of samples that must be generated to get one hit
in the middle bin. There the level corresponds to y = 0.5 and
hits in bin at y = 0.5 Δty=0.5 Δy Δy 1
= = = = N . (10.3)
total samples Tsw /2 π y − y2 π /2 π 2 /2
With a sine wave the number of samples is π /2 times larger than when applying a
sawtooth signal. To obtain an accuracy of 0.1 LSB in INL and DNL a minimum of
10 × π 2N /2 samples are required.
10.2.2 Harmonic Behavior
The same sine waves allow to measure harmonic distortion and related qualities
(intermodulation, spurious-free dynamic range, etc.) as well as the signal-to-noise
ratio. Fourier transformation of the output sample series allows to generate a
frequency diagram; Fig. 10.8. Many Fourier algorithms require that the period in
which the data is measured contains both an integer number of signal periods as well
as an integer number of sample periods; see Fig. 10.9. If this condition is not met,
the resulting signal will show side lobes, making the interpretation of the Fourier
result tedious. This phenomenon is called frequency leakage and is illustrated in
Fig. 10.10.
A second pitfall can occur if the sample rate is a simple multiple of the signal
frequency. Under stable signal conditions only a limited number of the levels in the
conversion process will be used. The evaluation of the converter is based on the
repetition of the same limited sequence of measurements and adds no information
on the levels that are missed; see Fig. 10.11.

9. 10.2 Measurement Methods 477
Fig. 10.8 Dynamic measurement of an analog-to-digital converter on intermodulation at f s =
100 MHs/s
Fig. 10.9 The measured period of a signal is expanded on both sides to enable a fourier
transformation. If the signal and the sample frequency do not fit to the window (below) frequency
leakage will occur
The basic requirement for a good test that avoids both problems is called the
“coherent testing” condition:
Ms Msignal
Tmeas = = , (10.4)
fs fsignal

10. 478 10 Characterization and Specification
Fig. 10.10 Frequency leakage because of one missing sample: left: 4,000 samples, right plot:
3,999 samples
Fig. 10.11 If the sample rate is an integer multiple of the sample rate, a part of the measured
samples are simple duplicates of the earlier sequence. In the frequency domain this may lead to the
masking of harmonics behind other harmonics or behind the fundamental frequency
where Msignal equals the number of input signal periods and Ms the number of
sample periods. If both integers are mutually prime no repetition of test sequences
will occur. Mutual prime or co-prime means that the largest common divisor of
Msignal and Ms is 1. The total measurement period is given by Tmeas . The measure-
ment period is inversely proportional to the frequency resolution or the frequency
“binning” of the Fourier transform. It is therefore necessary to choose a sufficiently
large Msignal , Ms , and Tmeas .
The discrete Fourier transform creates Ms /2 + 1 frequency bins of a size
1/Tmeas = fs /Ms . Both bins at 0 and at fs /2 are counted. A spectrum analyzer
often provides the option to define the bin size by means of the “resolution
bandwidth” parameter. If this value is set, automatically the measurement period
will be adjusted. The energy in the time-discrete signal is distributed over these
frequency bins. If energies from different phenomena (e.g., a harmonic component
and a folded component) end up in the same bin, the signal strength of these
components will add up or extinguish. A finer frequency grid can be obtained by
increasing the number of samples by increasing the measurement period Tmeas .
Figure 10.12 compares spectra taken with 200 and 2,000 samples.
Example 10.3. Explain the noise floor in Fig. 10.12.

11. 10.3 Self Testing 479
Fig. 10.12 Increasing the measurement period and the number of samples by a factor of 10,
reduces the bin size with that factor and lowers the noise floor by 10 dB
Solution. The 8-bit analog-to-digital converter has a theoretical maximum signal-
to-noise ratio of 1.76 + 8×6 dB = 49.8 dB. A measurement and Fourier transform
with 200 samples will result in 101 bins. The quantization energy in Fig. 10.12 is
distributed over these 101 bins, so the “noise floor” in the spectrum is expected at
a 100 × lower energy level: at 49.8 +10 log(100) dB≈ 70 dB below the fundamental
frequency. A tenfold increase will lead to a 10 times lower amount of energy per
bin. In a spectral plot the noise floor will drop by 10 dB.
Example 10.4. An ADC is tested during 1 ms at a sampling speed of 20 Ms/s; the
performance at 3 MHz signal frequency is required. Calculate an appropriate set of
test conditions.
Solution. With fs = 20 Ms/s and Tmeas = 1 ms, a total of N = 20, 000 samples
is generated. For a 10-bit ADC this would allow an accuracy of approximately
0.1 LSB. A 3 MHz input sine wave would show 3,000 periods, and no coherent
conditions can be observed. Changing the input frequency to 2.999 MHz will do. At
a test period of 1 ms, the spectral resolution (frequency bin) is 1/Tmeas = 1 kHz.
10.3 Self Testing
In complex systems sometimes forms of self-testing are necessary. Think of sensor
systems that need calibration in places that are difficult to reach. In another example
there is a liability aspect to the measurement equipment and the usability of the
converter must be established in situ (e.g., in a drilling head at 2 km below the earth’s
surface). Considerations for the implementation of self-test are:
• Complexity versus functionality: it may be sufficient to establish correct connec-
tivity of the converter. A simple block wave may be sufficient to test.
• Independence: no test may lead to a positive result because one error has the
same effect on the test circuit as on the converter. Using the same reference for
the converter as for the test circuit will disable proper detection of reference
deviations.

12. 480 10 Characterization and Specification
• The cost of error detection are repair facilities present, or can redundancy lead to
a solution (e.g., take a two-out-of-three vote).
• A parametric test can only be performed if somehow accuracy of the test signal
is provided. So self-tests create the need for having somewhere a more accurate
reference.
Self-testing can be implemented in systems where both a receive and a send
chain are present. In a 2.4 GHz transceiver, such a “loop-back” facility feeds a
fraction of the transmit power into the receiver. Proper test sequences applied to
the digital-to-analog converter input in the send chain allow a functional self-test
and also a few parameters can be evaluated. Another example of self-testing comes
from systems where it is impossible to approach the converter. For seismic purposes
ships drag large seismic arrays of cables with sensor interfaces. These arrays span
several hundreds of meters. Before a measurement is taken the quality of the
total interface chain is tested by means of built-in-self-test circuits. It is expected
that these professional developments of self-testing in some years will result in a
considerable improvement of the performance of self-test methods.
Example 10.5. A 10 bit ADC needs to be tested dynamically at 40 Ms/s in a DSP
based environment. (a) Determine the minimum test time needed to have accessed
all codes. (b) Why is it important that all codes have been accessed? There is 1 ms
test time available for the FFT. (c) Determine the input frequency at the Nyquist
edge for a good test. (d) What is the number of bins in the FFT? (e) Determine
the approximate noise level seen in the FFT plot. (f) What can be the technical
disadvantage of a long test time?
Solution. With 25 ns clock period a ramp signal will take 1024 × 25 ns = 25.6 μs.
In case a sinusoidal signal is used 40 μs is needed. Probably the DSP processing will
limit this test. All codes need to be accessed to be sure there are no missing codes.
A 1 ms FFT period results in a 1 kHz FFT bin size. For a 40 Ms/s sample rate and a
19.999 MHz input signal, N = 40,000 and M = 19.999 which numbers are mutually
prime. The number of bins in the FFT is 40, 000/2 + 1 = 20,001 bins of 1 kHz. The
10-bit converter should have an ideal noise level at 10 × 6 + 1.76 = 62 dB. If this
noise level is spread over 20,000 bins the level will drop another 1010 log(20, 000) =
43 dB. The total quantization noise level can reach −105 dB, so most likely some
thermal noise source will dominate. A long test period allows to perform a detailed
FFT that may reveal more details of the analog-to-digital converter’s performance.
Exercises
10.1. Compare the advantages and disadvantages of testing the performance of
an analog-to-digital converter by connecting a high-performance digital-to-analog
converter to the output or by analyzing the digital output in a signal processor.
10.2. Propose a sine-based equivalent test method for a digital-to-analog converter.

13. Exercises 481
10.3. The histogram measurement method uses a sine wave. Set up a test scheme
along the same lines using a uniform distributed random signal.
10.4. Can a sigma–delta modulator be tested with a histogram method?
10.5. An 8-bit 20 Ms/s analog-to-digital converter is tested during 0.1 ms with a
half-scale sine wave. The result is processed via an FFT. Make a drawing of the
expected FFT result.
10.6. A 6-bit ADC needs to be tested dynamically at 4 Gs/s in a DSP-based
environment. Determine the minimum test time needed to have accessed all codes.
There is 40 μs test time available for the FFT. Determine the input frequency at the
Nyquist edge for a good test. What is the number of bins in the FFT? Determine the
approximate noise level of the FFT.
10.7. An 8-bit 600 Ms/s analog-to-digital converter is used in a communication
system where a spurious-free dynamic range of 80 dB in 2 MHz bandwidth is
required. What test is required.
10.8. An analog-to-digital converter is part of a system on silicon. The sample clock
is generated on chip and cannot be accessed separately. Define a method to quantify
the jitter of the clock.