Punit Shah is an Electrical Engineering graduate student at Arizona State University seeking an internship or co-op position in mixed signal circuit design and verification. He has strong academic experience in areas such as VLSI design, hardware design verification, computer architecture, and analog integrated circuits. Some of his academic projects include designing a memory controller, ALU components, a MIPS processor, and a 4x4 router for a NOC network. He implemented a pseudo LRU cache replacement policy and designed a two-stage opamp.

1. PUNIT SHAH
(480)-626-3240 9125 Truman Street,San Diego,CA92129 pshah15@asu.edu
www.linkedin.com/in/punitshah13
Electrical EngineeringGraduatestudentatArizonaStateUniversity specializingin Electronicsand Mixed Signal CircuitDesign,seekinginternshipand-
or Co-op positionin thefieldof Mixed Signal CircuitDesign& Verification,ASIC and SOC architecture, RTL abstraction, functional verification and
other related areas; having strong academic and research experience in areas related to
• VLSI Design • HardwareDesignand Verification Languages • Computer Architecture • AnalogIntegrated Circuits
EDUCATION
Master ofScience – ElectricalEngineering (Expected May2016)
Arizona StateUniversity,Tempe,AZ GPA 3.33/4.0
Courses:Spring2015:VLSI Design,HardwareDesignand Verification Languages (HDVL),Nano Fabrication/Characterization
Fall 2014:Digital Systems and Circuits (DSC),AnalogIntegrated Circuits (AIC),Computer Architecture
Bachelor of Technology – Electrical and Electronics Engineering May 2014
VITUniversity,Vellore,India GPA 8.36/10.0
TECHNICAL SKILLS
Languages: C, C++, Verilog, System Verilog, VHDL, Assembly Language, MIPS assembly, Python, Shell Scripting, Perl/Tcl
Application Tools: CadenceVirtuoso LayoutEditor,CadenceEncounter (Place/Route),CadenceAnalogDesignEnvironment, Cadence Spectre, Aldec
Riviera Pro, Modelsim, Synopsys Prime Time-Static Timing Analysis, HSPICE, PSPICE, Simple Scalar, Xilinx ISE, MATLAB, LABVIEW
Operating Systems: Red Hat LINUX, Windows 7, 8, MAC Leopard IOS
Graduate Research Assistant atArizonaStateUniversity (Professor John Brunhaver) February 2015 - Present
Optimizing thedarkroomcompiler (compilinghigh level imageprocessingcodeinto hardwarepipeline) using floating point image data to enhance
edge and corner detectionfor computer visionapplications;EmployingLogarithmic FloatingPointUnitGenerator to convert the image matrices for
stencil Kernel operationssuchasconvolution.All operationson imagematrices areperformed using Python scripting including Numpy, Scipy and
Matplot tools. Second Phase is estimating the energy efficiency of the floating point unit design for different precision points
ACADEMIC PROJECTS
Designingand testingofa memorycontroller for MIPS/ARM Interface usingSystem VerilogProgramming(HDVL) Spring2015
 32 bit address space divided amongst SDRAM (2GB), ROM (1KB), SRAM (1KB) and an I2C four slave master
 Designed theI2C mater slavewith finitestatemachine principlehavingread and writeoperationsthrough half duplex serial data bus with
core clock operating at 100MHZ and I2C clock operating at 10MHZ
ALU(Arithmetic/LogicalUnit)Component Design for a16-bit ProcessorusingVerilogHDL (HDVL) Spring2015
 Created building blocks of ALU viz. 4-bit Ripple Carry Adder, 16-bit Carry Select Adder, 16-bit Signed Multiplier and 16-bit Shifter
 Verified these ALU components using test cases and simulated waveforms showing full functionality using Aldec Riviera Pro 
Designed and Verification ofMIPS ISA using System Verilog(HDVL) Spring 2015
 Designed 32 bitnon pipelined MIPS ArchitectureinSystemVerilog
 Performed functional verification of theMIPS ISAthrough simulationin Aldec RivieraPro for nonpipelined MIPSISA
Designed an Object Oriented Verification EnvironmentusingSystem VerilogClasses (HDVL) Spring2015
 Verification Setup included classesfor Packetin,Driver,DUT,Receiver,Packetoutand scoreboard.Assertionsused to check thefailurepoint
 Verified Combinational Logic(AND gate) and Sequential Logic(DFF)
Designed a 16 entry,16 bit wide registerfile with one read and one writeport (VLSIDesign) Spring2015
 Cadence virtuoso for Layout, DRC/LVS, schematic, netlist and partial extraction. Timing verification using Hspice
 Optimized the design through diffusion sharing of access transistors to reduce load capacitance on the bitlines and layout ar ea
 RTL level abstraction for the register file in Modelsim and a testbench with randomized test cases
Designingand Testingofa 4*4 router for aNOC network usingautomated design flow for 32nmTechnology(VLSIDesign) Spring2015
 RTL level design for individual components of the router viz. FIFO, Priority Encoder, Flex Switch and an Arbiter using Modelsim
 Cadence RC compiler for synthesizing the Tcl script containing standard cell library, verilog design code and design constrai nts.
 Encounter tool for place/route and Prime time Synopsys tool for generating worst case timing report and power report
 Created verilog testbench for testing synthesized and post encounter verilog netlist
Implementation ofPseudo LRUReplacementpolicyin simple scalar (ComputerArchitecture) Fall 2014
 Implemented Treebased Pseudo LeastRecently Used cachereplacementpolicy by modifyingthesimplescalar x86 sourcecodefor a64KB
L1 data cacheand L1 Instruction cachewith varyingassociativity usingC programming
 Compared PLRUwith LeastRecently Used andFIFOreplacementpolicy for Test-math,Anagram, Go and Perl benchmarks usingC Program
Two Stage OpAmp design usingTSMC 0.25um technologyin Cadence AnalogDesign Environment(AIC) Fall 2014
 Designed a CMOS two stage OpAmp with miller and lead compensation to drive a load of 10pF parallel 1Kohm
 Achieved a GBW of 84.59MHz with DC gain of 83.23dB, phase margin of 60dB and input referred noise of 80.87 nV/sqrt (Hz)
PROFFESIONAL EXPERIENCE
Summer Internat Aash Cube LightingPrivate Limited (India) June 2013
 Hands on experienceinsolderingdifferentcomponentson a LED driver circuit
 Tested the driver circuitas per thetestplan usingvariablepower supply andestimated thepower dissipation and energy consumption