Dws 8.4 manual_final_27012013

Copyright 1985-2013 Piero Belforte , Giancarlo Guaschino

DWS
Digital Wave Simulator

RELEASE 8.4

USER'S MANUAL

i


Copyright 1985 – 2013 Piero Belforte, Giancarlo Guaschino

This document contains proprietary information of Piero Belforte and Giancarlo
Guaschino, Torino, Italy.

DWS (Digital Wave Simulator) is a trademark of Piero Belforte and Giancarlo
Guaschino.

DWV (Digital Wave Viewer) is a trademark of Piero Belforte and Giancarlo
Guaschino.

SWAN (Simulation by Wave ANalysis) is a trademark of Piero Belforte.

All rights are reserved.

The contents of this document may not be copied or reproduced in any form
without the express prior permission of Piero Belforte and Giancarlo Guaschino.
Piero Belforte and Giancarlo Guaschino shall not be liable for errors contained
herein and the information contained in this document is subject to change
without notice.

Piero Belforte's info can be found at http://www.linkedin.com/in/pierobelforte

SWAN/DWS story with publications links is available here:
https://docs.google.com/file/d/0Bx-ZqV10CSiNaG5yaW1JWi1EWjQ/edit

ii

Table of Contents DWS

TABLE OF CONTENTS

TABLE OF CONTENTS ................................................................................................................. V

CHAPTER 1. GENERAL FEATURES ....................................................................................1-1

1.1 INTRODUCTION ...................................................................................................................1-2
1.2 GENERAL USE CONSIDERATIONS ........................................................................................1-3
1.2.1 Time Step ....................................................................................................................1-3
1.2.2 Elements .....................................................................................................................1-4
1.2.3 Two-Port Element Conversion ...................................................................................1-6
1.2.4 Reference Impedance .................................................................................................1-9
1.2.5 Delay Discretization ................................................................................................1-10
1.2.6 DWS Operation ........................................................................................................1-12
1.2.7 Memory Requirements .............................................................................................1-15
1.3 CIRCUIT DESCRIPTION ......................................................................................................1-16
1.4 INPUT FORMAT .................................................................................................................1-17
1.5 OUTPUT FILE ....................................................................................................................1-18
1.6 REPORT FILE .....................................................................................................................1-21
1.7 STARTING DWS ................................................................................................................1-22

CHAPTER 2. PASSIVE ELEMENTS ......................................................................................2-1

2.1 LINEAR RESISTORS .............................................................................................................2-3
2.2 PIECE-WISE LINEAR RESISTORS .........................................................................................2-4
2.3 TIME-CONTROLLED LINEAR RESISTORS .............................................................................2-6
2.3.1 DC Resistor Function .................................................................................................2-9
2.3.2 Pulse Resistor Function ...........................................................................................2-10
2.3.3 PulsePoly Resistor Function ...................................................................................2-11
2.3.4 PulseErfc Resistor Function ....................................................................................2-12
2.3.5 Erfc Resistor Function .............................................................................................2-13
2.3.6 Delta Resistor Function ...........................................................................................2-14
2.3.7 Sinusoidal Resistor Function ...................................................................................2-15
2.3.8 Piece-Wise Linear Resistor Function .......................................................................2-16
2.3.9 PulsePwl Resistor Function .....................................................................................2-17
2.3.10 File Resistor Function ............................................................................................2-18
2.3.11 PulseFile Resistor Function ...................................................................................2-19

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2.4 VOLTAGE-CONTROLLED RESISTORS ................................................................................ 2-21
2.5 CURRENT-CONTROLLED RESISTORS................................................................................. 2-25
2.6 STATIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED RESISTORS ... 2-29
2.6.1 Linear Static Transfer Function.............................................................................. 2-29
2.6.2 Piece-Wise Linear Static Transfer Function ............................................................ 2-30
2.6.3 File Static Transfer Function ................................................................................... 2-31
2.6.4 Threshold Static Transfer Function ......................................................................... 2-32
2.6.5 Hysteresis Static Transfer Function......................................................................... 2-33
2.7 DYNAMIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED RESISTORS2-34
2.7.1 Unit-step Dynamic R................................................................................................ 2-35
2.7.2 S-plane Dynamic Transfer Function ........................................................................ 2-38
2.7.3 Z-plane Dynamic Transfer Function ....................................................................... 2-40
2.8 LINEAR CAPACITORS ........................................................................................................ 2-42
2.9 LINEAR INDUCTORS .......................................................................................................... 2-44
2.10 COUPLED INDUCTORS ..................................................................................................... 2-46
2.11 UNBALANCED TRANSMISSION LINES .............................................................................. 2-48
2.12 BALANCED TRANSMISSION LINES .................................................................................. 2-50
2.13 UNIT-DELAY TRANSMISSION LINES ............................................................................... 2-52
2.14 IDEAL TRANSFORMERS ................................................................................................... 2-54
2.15 JUNCTION DIODES .......................................................................................................... 2-56

CHAPTER 3. INDEPENDENT SOURCES ............................................................................. 3-1

3.1 INDEPENDENT VOLTAGE SOURCES (THEVENIN EQUIVALENT) ........................................... 3-3
3.2 INDEPENDENT CURRENT SOURCES (NORTON EQUIVALENT) .............................................. 3-4
3.3 INDEPENDENT SOURCE FUNCTIONS .................................................................................... 3-5
3.3.1 DC Source Function .................................................................................................. 3-5
3.3.2 Pulse Source Function ............................................................................................... 3-6
3.3.3 PulsePoly Source Function ....................................................................................... 3-7
3.3.4 PulseErfc Source Function ........................................................................................ 3-9
3.3.5 Erfc Source Function ............................................................................................... 3-10
3.3.6 Delta Source Function ............................................................................................. 3-11
3.3.7 Sinusoidal Source Function ..................................................................................... 3-12
3.3.8 Piece-Wise Linear Source Function ........................................................................ 3-13
3.3.9 PulsePwl Source Function ....................................................................................... 3-14
3.3.10 File Source Function ............................................................................................. 3-15
3.3.11 PulseFile Source Function..................................................................................... 3-16
3.4 SOURCE FUNCTIONS WITH A PARAMETER CONTROLLED BY A NODE VOLTAGE ............... 3-18

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3.5 BINARY DIGIT SEQUENCE .................................................................................................3-19
3.5.1 Sequence Definition .................................................................................................3-20
3.5.2 Single Sequence........................................................................................................3-21
3.5.3 Periodic Sequence ....................................................................................................3-22
3.5.4 Burst Sequence .........................................................................................................3-22

CHAPTER 4. CONTROLLED SOURCES..............................................................................4-1

4.1 VOLTAGE-CONTROLLED VOLTAGE SOURCES .....................................................................4-3
4.2 VOLTAGE-CONTROLLED CURRENT SOURCES .....................................................................4-5
4.3 CURRENT-CONTROLLED VOLTAGE SOURCES .....................................................................4-7
4.4 CURRENT-CONTROLLED CURRENT SOURCES .....................................................................4-9
4.5 MULTIPLYING VOLTAGE-CONTROLLED VOLTAGE SOURCES ............................................4-11
4.6MULTIPLYINGVOLTAGE-CONTROLLEDCURRENTSOURCES................................................................4-13
4.7 STATIC TRANSFER FUNCTIONS .........................................................................................4-15
4.7.1 Linear Static Transfer Function ...............................................................................4-15
4.7.2 Piece-Wise Linear Static Transfer Function ............................................................4-16
4.7.3 File Static Transfer Function ...................................................................................4-17
4.7.4 Threshold Static Transfer Function .........................................................................4-18
4.7.5 Hysteresis Static Transfer Function .........................................................................4-19
4.8 DYNAMIC TRANSFER FUNCTIONS FOR VOLTAGE OR CURRENT-CONTROLLED SOURCES ..4-20
4.8.1 Unit-step Dynamic Response ...................................................................................4-21
4.8.2 S-plane Dynamic Transfer Function ........................................................................4-24
4.8.3 Z-plane Dynamic Transfer Function ........................................................................4-26

CHAPTER 5. S-PARAMETER ELEMENTS .........................................................................5-1

5.1 INTRODUCTION TO S-PARAMETER ELEMENTS ....................................................................5-2
5.2 1-PORT ELEMENTS DEFINED BY S-PARAMETERS ................................................................5-4
5.6 S-PARAMETER DESCRIPTION ..............................................................................................5-8
5.6.1 Piece-Wise Linear S-Parameter Description .............................................................5-8
5.6.2 File S-Parameter Description ..................................................................................5-10

CHAPTER 6. ADAPTORS ........................................................................................................6-1

6.1 GENERAL FEATURES ...........................................................................................................6-2
6.2 SERIES ADAPTORS ..............................................................................................................6-3
6.3 BIMODAL ADAPTORS ..........................................................................................................6-5

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6.4 MULTIMODAL ADAPTORS................................................................................................... 6-7

CHAPTER 7. SUBCIRCUITS AND CHAINS ........................................................................ 7-1

7.1 GENERAL FEATURES .......................................................................................................... 7-2
7.2 SUBCIRCUITS ...................................................................................................................... 7-3
7.2.1 .SUBCKT Statement ................................................................................................... 7-3
7.2.2 .ENDS Statement........................................................................................................ 7-4
7.2.3 Subcircuit Calls ......................................................................................................... 7-4
7.3 CHAINS OF CELLS ............................................................................................................... 7-5
7.3.1 .CELL Statement ........................................................................................................ 7-5
7.3.2 .ENDC Statement ....................................................................................................... 7-6
7.3.3 Cell Calls ................................................................................................................... 7-6

CHAPTER 8. CONTROL STATEMENTS ............................................................................. 8-8

8.1 .OPTIONS STATEMENT .................................................................................................... 8-9
8.2 .TRAN STATEMENT ......................................................................................................... 8-10

viii

DWS General Features

Chapter 1
General Features
1.

1.1 Introduction

1.2 General use considerations

1.2.1 Time step

1.2.2 Elements

1.2.3 Two-port element conversion

1.2.4 Reference impedance

1.2.5 Delay discretization

1.2.6 DWS operation

1.2.7 Memory requirements

1.3 Circuit description

1.4 Input format

1.5 Output file

1.6 Report file

1.7 Starting DWS

Chapter 1 1-1


1.1 Introduction
DWS (Digital Wave Simulator) is a new conception simulator implemented
with the aim of dealing with the emerging needs of advanced electronic design in
a more effective way. It integrates simulation capabilities at different levels:
physical, electrical, timing, logic (switch-level) and system. Using advanced
concepts and unique powerful DSP (Digital Signal Processing) wave algorithms
instead of classical Nodal Analysis (NA), DWS can solve design problems
where other tools (SPICE-derived and transmission-line simulators) fail. The
major causes of these failures are known to be: limited capabilities of circuit
modeling, convergence problems and/or excessive computing times when
working with small time steps or high Q circuits, limited efficiency in dealing
with propagation delays and distributed parameter environments, topology
limitations and difficulties in utilizing different abstraction levels in the same
simulation. To overcome these drawbacks DWS is based on a very advanced
simulation engine which supports new hardware modeling concepts and
techniques with particular emphasis on new high-speed circuits and systems.
DWS was created by engineers to solve actual design needs. The use of wave
variables, instead of classical voltages and currents of NA, leads to an extremely
accurate and fast models of TRANSMISSION LINES (mono or multimodal).
As known, NA-based simulation engines suffer of poor modeling capability of
signal propagation effects because NA assumes no signal propagation in the
circuit under analysis. This last assumption is no more valid for dealing with
modern high-speed circuitry when digital signal transition time is of the same
order of magnitude of physical propagation delays.
Very accurate and efficient models of new electronic devices (active and
passive) can be directly obtained by means of time-domain experimental
characterizations with no need of knowledge of the internal structure of them
(BTM: Behavioral Time Modeling technique). Multiport time-domain S-
parameter blocks can be easily built up starting from actual TDR (Time Domain
Reflectometer) measures using efficient PWL (PieceWise Linear) description of
behaviors.
Due to outstanding STABILITY of DWS wave algorithms, there is no need of
strict CAUSALITY and PASSIVITY features of S-parameter behaviors. In this
way, very accurate and stable models of lossy interconnections (2-port, 4-port)
can be easily built up.

Chapter 1 1-2


PWL behaviors can be used to describe non-linear resistors, allowing the user to
simulate non-linear circuits that are not affordable with conventional NA
simulators. I/O macromodels of digital integrated circuits, as the IBIS standard
models, can be easily supported. New classes of non-linear circuits including
CHAOTIC circuits and systems can be easily simulated by DWS without
iterations and with no convergence problems. Due to its outstanding speed,
Millions or even Billions of samples can be calculated in short times.
Very fast and accurate Transmission Line models open the way to extremely
efficient Transmission Line Modeling (TLM) of actual devices including 2-D
lossy signal propagation effects.
Working at fixed time step, DWS is fully Nyquist criterion compliant, while NA
simulators are not.
Using wave variables, DWS allows the user to monitor a complete set of
variables at each node of the circuit including Voltage, Current, Power, Incident
and Reflected Waves etc. without any addition of extra elements as required by
NA simulators.
DWS algorithms are so fast and powerful that very complex networks with
hundred thousand elements can be dealt with in seconds or minutes even for
hundred thousand out samples. For this reason they have been utilized by major
international organizations for fast and accurate POST-LAYOUT simulations of
complex Multiboard systems including 2-D models of Power Distribution
network and accurate 4-port IBIS models of active devices I/Os.
For the above mentioned reasons, DWS can be considered something more than
simply a simulator: it is also powerful modeling and simulation environment with
a 4-decade long application history to state-of-the-art circuits and systems.
In order to shorten training time, DWS utilizes a SPICE-like syntax for writing
out network description. Powerful primitives permit a very efficient description
of network elements and stimulus signals. PieceWise Linear (PWL) fittings
and stored samples coming from previous simulations or measurements can be
used as behavioral descriptions. In the same way the outputs coming from other
analog simulators can be utilized to get DWS-compatible behavioral models.
DWS and its companion graphical post-processor DWV (Digital Wave Viewer)
belongs to the SWAN modeling and simulation environment.

Chapter 1 1-3


1.2 General Use Considerations
Even if DWS use is very similar to SPICE, its internal operation is completely
different from the conventional analog simulators using Newton-Raphson
iterative loops and NA sparse-matrix techniques. DWS utilizes a brand-new
technique that converts the electrical network into a numerical equivalent
operating like a true DSP (Digital Signal Processor) [1]. This approach gives the
user several advantages including very high simulation speed, robustness
(iterative procedures and convergence problems are virtually avoided), and the
capability of simulating high complexity networks. DWS's performance
advantages are more and more evident as this complexity increases and will
further grow with the increase of computer's power.
To operate DWS correctly, a few issues have to be taken into account. These
issues will be briefly dealt with in the following.

1.2.1 Time Step

Being a DSP, DWS operation requires a fixed time step. This time step is defined
by the user in the .TRAN statement (see also Chapter 8), and its choice is very
important because it greatly affects both accuracy and simulation speed.
In any case, the Nyquist criterion has to be taken into account, so that the
simulation time step is strictly correlated with the bandwidth of the simulated
system and of its stimuli.
Another consideration affecting the time-step choice is related to the delays of
elements belonging to the simulated network. If no DELAYMETH option is
specified, all the delays are rounded to an integer multiple of time step, so that no
delay error occurs if each specified delay is an integer multiple of the chosen
step. When this situation is not verified, as in the case of small delay differences
between elements, due for instance to different mode propagation velocities in
coupled lines, it is suggested to use the DELAYMETH=INTERPOLATION
.option that operates some kind of interpolation in the delay evaluation, so that
the simulation error is reduced even if a very small time step isn't used.
Simulation error increases roughly with the square of the time step [2]. When in
doubt about the choice, it is suggested to run a reference simulation with a small
time step (e.g. 1/10 of the selected one) in order to compare the DWS's responses
with this reference and to have an evaluation of the simulation error.

Chapter 1 1-4


1.2.2 Elements
.
DWS's simulation engine maps each element and each node belonging to the
source netlist into a numerical equivalent which exchanges signals with the rest
of the network through its ports..
A port of an element is an internal DWS structure basically carrying the
following variables.:

A: port's incident voltage wave
B: port's reflected voltage wave
Z0: port's reference impedance

where the voltage is normally referenced to ground (node 0).

Generic port N
port N
N I
A A

B electrical digital
V wave
Z0 network network
B
(0)
Z0

electrical representation wave representation

At each element's port the following wave equations. apply:

V=A+B stating that the port voltage is the sum of the port's
incident and reflected voltage waves.

I = (A - B) / Z0 stating that the current entering the port is the
difference between the incident and reflected
voltage waves divided by the port's reference
impedance Z0.

The reference impedance of each port is determined by DWS during a setup
phase before the beginning of the real simulation run when the signals at each
port are calculated. If DWS cannot determine all the port reference impedances,

Chapter 1 1-5


proper warning message will be issued so that the user will be able to enter some
more information (like the element's reference impedance) or to introduce in the
netlist some decoupling elements like unit delays..
DWS can deal with elements having more than two ports. Element ports cannot
be left open. An external resistor of practically infinite resistance (e.g. 1E9) can
be connected between the open port and ground.
In order to maintain SPICE compatibility, an element's port is normally identified
in the source netlist by a node identifier (integer number). The reference node 0
(ground) of the port is specified only if it is necessary to have SPICE
compatibility or to avoid misunderstanding.
Examples:

R1PORT 1 0 1K
1 specifies a 1k one-port resistor. The port
identifier is 1 corresponding to node 1. Here
PORT1 R1PORT the ground node 0 is specified to have
SPICE syntax compatibility.

R2PORT 1 2 10K

1 R2PORT 2 specifies a 10k two-port resistor. The port identifiers
PORT1 PORT2
are 1 and 2 corresponding to node 1 and node 2
respectively. Here the ground node 0 is NOT
specified to have SPICE syntax compatibility.

AS3PORT 1 2 3
specifies a three-port element (series
1 2
adaptor). The port identifiers are 1, 2 and 3
PORT1 PORT2 corresponding to node 1, node 2 and node
3 3 respectively. Here the ground node 0 is
PORT3
NOT specified because SPICE
compatibility is not required (SPICE
doesn't allow the use of this kind of adaptors).

Chapter 1 1-6


The two-port unbalanced transmission-line elements accept both SPICE-like
syntax where the node 0 is specified and the short syntax where it is not
specified. So:

T2PORT 1 2 Z0=50 TD=1NS (short DWS syntax)

or

T2PORT 1 0 2 0 Z0=50 TD=1NS (Spice-like syntax)

are the two ways allowed to describe the same transmission-line.

T2PORT
1 2

PORT1 PORT2

1.2.3 Two-Port Element Conversion
.
Before starting the simulation run, DWS converts some types of two-port
elements of the flattened netlist into one-port elements connected to the third port
of a series adaptor. This automatic conversion applies in particular for the
following two-port elements:

- Resistors (including nonlinear and controlled resistors)
- Capacitors
- Voltage sources (including controlled sources)
- Current sources (including controlled sources)
- Diodes

Moreover, DWS converts the balanced transmission lines of the flattened netlist
(four-port elements) into two-port transmission lines connected to the third port
of two series adaptors.
A similar conversion is applied to balanced ideal transformers.

For example, the two-port resistor of the source netlist:

Chapter 1 1-7


R2PORT 1 2 10K

will be converted in the two following elements:

AS.R2PORT 1 2 3
R2PORT 3 0 10K

1 2

1 2 3

R2PORT R2PORT

In particular for two-port capacitors this is equivalent to use by default the so
called "stub model" [2] which in turn means to apply the trapezoidal method of
integration.
By default the two-port inductance is NOT converted in this way. Instead a so
called "link-model" is used to deal with inductances [2]. In this way DWS by
default processes a two-port inductance as a unit-delay transmission line with
impedance Z0=L/TSTEP where TSTEP is the simulation time step. If the user
prefers the stub model (trapezoidal integration method), he can define the two-
port inductance in the source netlist file as a series adaptor with a one-port
inductance connected to its third port. For example, if the user specifies the
following statement:

L2PORT 1 2 1NH

DWS deals with the inductance as a unit-delay transmission line of
impedance Z0=1E-9/TSTEP; if he specifies instead the following statements:

ASL 1 2 3
L1PORT 3 0 1NH

Chapter 1 1-8


DWS deals with the inductance using the trapezoidal method equivalent to a
shorted stub of Z0=2E-9/TSTEP and TD=TSTEP/2 connected between nodes 1
and 2.

Z0=L/TSTEP
1 TD=TSTEP 2
default

"link" model
1 2
1 2
L2PORT
trapezoidal
3
Z0=2L/TSTEP
TD=TSTEP/2

"stub" model

For the balanced transmission line, the automatic conversion is carried out for both its
balanced ports, as shown below:

TBAL 1 2 3 4 Z0=50 TD=1NS

1 3

2 4

is automatically converted in:

AS.TBAL 1 2 10
TBAL 10 0 20 0 Z0=50 TD=1NS
AS.TBAL 3 4 20

1 3
10 20

2 4

Ports 10 and 20 assume the meaning of balanced ports corresponding to the
couples of nodes 1,2 and 3,4 respectively.

Chapter 1 1-9


During the automatic two-port conversion, DWS also carries out a search for
parallel connections involving elements belonging to the types previously
mentioned. If two or more elements of these types are found to be connected in
parallel, this configuration will be automatically converted by means of a single
series adaptor, so that all the converted 1-port elements will be connected in
parallel at the third port of it.
Example:

R 1 2 100 R N 0 100
C 1 2 1NF AS.P.R 1 2 N
D 1 2 DMOD C N 0 1NF
D N 0 DMOD

AS.P.R
1 2
R

N
1 C 2

C D
R
D

The identifier of the series adaptor will be AS.P.elname (P means parallel) where
elname is the name of the element connected in the parallel block that first has
been descripted in the netlist.

1.2.4 Reference Impedance
.
As previously mentioned each element's port needs to have its reference
impedance defined by DWS before starting the simulation run. Some elements
like the piecewise-linear resistor or the diode require that the value of the
reference impedance are defined by the rest of the network connected to them. In
some cases, DWS is unable to determine Z0 due to a particular topology of the
network. This can happen, for instance, when two or more non-linear elements
are directly connected together. In this case DWS stops before starting the
simulation and issues a message identifying the problem and the location of the

Chapter 1 1-10


involved elements. At this point the user can define Z0 directly in the nonlinear
element's statement or add unit-delay transmission lines to cut the direct
connection causing the problem. In both cases an element is added to the original
network and its additional effect vanishes decreasing the time step. In general
this additional effect is lower if the impedance is defined within the element's
statement.

1.2.5 Delay Discretization

Several DWS elements include an intrinsic delay whose value can be specified
by means of parameter TD. To perform the simulation, the input value will be
discretized on the basis of the selected simulation time step (TSTEP). No delay
error due to discretization will occur if all specified parameters TD are integer
multiple of simulation TSTEP.
Two delay discretization strategies are allowed depending on the DELAYMETH
option set by the user on the DWS input file:
- ROUNDING: this is also the default method if no DELAYMETH is
_
specified. If TD > 0.5 TSTEP the actual simulation delay
DTD (Discretized Time Delay) will be the nearest integer
multiple of the simulation timestep TSTEP, so that a
maximum error of 0.5 TSTEP will be caused by the delay
discretization.
_
- INTERPOLATION: if TD > 0.5 TSTEP the output of the actual delay block
will be obtained as linear interpolation between the outputs
generated by the two delays multiple of the time step
within which the given TD is comprised. This second kind
of approximation leads generally to an error lower than
pure rounding error.

In case the input parameter TD is set to a value < TSTEP including 0, the actual
discretized value for simulation will be set to TSTEP for both strategies.

Chapter 1 1-11


Input
TD, TSTEP

Y
TD < 0.5 TSTEP DTD = TSTEP
N

interpolation rounding
DELAYMETH

linear interpolation between DTD = n * TSTEP
the outputs On and On+1 so that
corresponding to the nearest
integer multiples of time step | TD - DTD | < 0.5 * TSTEP

Chapter 1 1-12


1.2.6 DWS Operation

Starting from the circuit description contained in the input file, DWS creates
sequentially three temporary files each generated from the previous one:

filename.t0: compressed netlist generated from the source netlist where each
statement is contained within a single line of text. The source lines
separated by the continuation character "+" at the beginning of the
line are joined together.

filename.t1: netlist after the subcircuit and chain expansion (flattened netlist).

filename.t2: netlist after the conversion of two-port elements into one-port
elements connected to a series adaptor. DWS simulates the circuit
as described in this temporary file. The report file is related to the
information carried by this netlist.

Syntax checks are performed at source netlist level. If a syntax violation is
detected, DWS stops and an error message containing the identifier of the
incorrect line is issued at the standard output, like:

Fatal Error : error message

On the basis of the network description contained in the flattened and converted
netlist (filename.t2), DWS builds up a node table where each node is classified
according to the number of connected element's ports.
If nodes connected to only one port (excluding control nodes) are detected, DWS
stops, and the following message will be issued at the standard output:

Fatal Error : floating node N in element elname

where N is the node with only one port and elname is the name of the element
connected to N. If floating control nodes of controlled elements are detected,
DWS stops, and the following message will be issued at the standard output:

Fatal Error : floating control node N

Upon the completion of node table and memory allocation procedure, DWS
starts a simulation scheduler which assigns the reference impedance to each

Chapter 1 1-13


element port. If some port impedance cannot be assigned due to a particular
topology of the network, the problem is located and the following error message
is issued at the standard output:

Fatal Error : network topology not allowed due to element elname

At this point, the user can add decoupling elements in the source netlist as
previously described (see section 1.2.4). In this way the user has a complete
information about the actual network he is going to simulate.
Upon completion of the scheduling process a message is issued at the standard
output and the true simulation run can begin.
After a digital network setup phase during which the calculation parameters of
elements and nodes are set, as well as the user's initial conditions (if so specified
by the UIC parameter in the .TRAN statement), the simulation loop starts.
Due to the outstanding robustness of DWS's algorithms, a simulation allowed to
start will reach its end without incurring in troubles like convergence or
numerical problems, that typically affect other products. These considerations
apply as well in the most complex simulations involving a very large number of
elements, that other analog simulators based on conventional algorithms can't
afford.
At the begin of the simulation run a CIRCUIT SIMULATION STARTED
message is issued at the standard output. A message will be also issued during
the simulation loop upon completion of one tenth of the simulation time window
(TSTOP/10). The CPU time required by DWS to complete each tenth of the time
window is strictly constant, so that the user can easily evaluate the amount of
time that will be required to complete the run. At each loop, corresponding to a
TSTEP increment of time, the digital network status is updated. The outputs
regarding the signals specified by the user in the .TRAN statement are stored
starting from TSTART and ending with TSTOP which also stops the simulation
loop.
At this point DWS outputs regarding the user selected waveforms are stored in
the file identified as filename.g. If the user has specified an output time step (by
means of the .TRAN parameter LIMPTS) not coincident with TSTEP, the
filename.g will store waveform samples obtained performing a linear
interpolation on the calculated samples.
Upon simulation run completion, the CPU time information including Specific
Elapsed Time (SET, see also 1.6) will be printed out on the standard output.

Chapter 1 1-14


1.2.7 Memory Requirements

The maximum allowed network complexity (see also 1.6) that DWS can process
in a single run is determined by the amount of RAM space available.
Because each element and node type has different memory allocation
requirement, the maximum allowed net complexity also depends on the particular
element mix and on net topology. For a typical mix, each thousand of elements
requires about 1Mbyte of RAM space, so that a 1Gbyte RAM personal computer
can roughly process 1 Million element nets (considering the memory used by the
system).

[1] Piero Belforte, Giancarlo Guaschino: “Electrical Simulation using digital
wave networks”, IASTED International Symposium, Paris June 1985.
[2] P.B.Johns,M.O'Brien:"Use of the transmission-line modeling (TLM) method
to solve nonlinear lumped networks", Radio & Electronic Eng., 1980, Vol.50,
No.1/2, pp.59-70.

Chapter 1 1-15


1.3 Circuit Description
DWS circuit description philosophy is derived from the standard simulator
SPICE. SPICE statement compatibility has been held as far as possible. In the
situations not dealt with by SPICE, DWS syntax is conceived as a superset of
SPICE syntax. The circuit to be analyzed is described to DWS by a set of
element statements, which define the circuit topology and element values, and a
set of control statements, which define the conditions of the simulation and the
simulation results the user wishes saved. Comments are statements which begin
with an asterisk "*" in column 1. They are for user documentation purposes only
and are ignored during simulation. Simulation control statements begin with a
dot "." in column 1. The last statement must be a .END statement. The order of
the remaining statements is arbitrary. Each element in the circuit is specified by
an element statement that contains the element name, the circuit nodes (port
identifiers, see also 1.2.2) to which the element is connected, and the values of
the parameters that determine the electrical characteristics of the element. The
first letter of the element name specifies the element type. The format for the
DWS element types is given in what follows. The strings XXXXXXX and
YYYYYYY denote arbitrary alphanumeric strings. For example, a resistor name
must begin with the letter R and can contain one or more characters. Hence, R,
R1, RS, ROUT, and R1TERM are valid resistor names.
Data fields that are enclosed in less than and greater than signs "< >" are
optional. All indicated punctuation (parentheses, equal signs, etc.) must be
specified.
Nodes names (port identifiers) must be positive integer numbers. The datum
(ground) node must be named "0". Every node must have at least two ports
except for control nodes. As mentioned in 1.2.4, the situations in which the
program cannot find the proper value for the reference impedance of an element
port are pinpointed and warning message containing involved element is issued.
In this case the user can insert an additional element, usually a unit-delay
transmission line, or specify the impedance within the element's statement.
Hierarchical circuit descriptions are possible through the use of subcircuits (see
also .SUBCKT statement) that operate exactly in the same way of SPICE.
An additional automatic description capability is offered by DWS by means of
chains (see also .CHAIN statement) allowing the user to build up a cascade
connection of whatever number of basic circuit cells defined in the same input
text.

Chapter 1 1-16


1.4 Input Format
The input format for DWS is of the free format type. Fields in a statement are
separated by one or more blanks, a comma, an equal "=" sign, or a left or right
parenthesis; extra spaces are ignored. A statement may be continued by entering
a + (plus) in column 1 of the following line; DWS continues reading beginning
with column 2.
A name field must begin with a letter (A through Z) and cannot contain any
delimiters.
A number field may be an integer field (12, -44), a floating point field (3.14159),
either an integer or floating point number followed by an integer exponent (1E-
14, 2.65E3), or either an integer or a floating point number followed by one of
the following scale factors:

T=1E12 G=1E9 MEG=1E6 K=1E3
M=1E-3 U=1E-6 N=1E-9 P=1E-12 F=1E-15

Letters immediately following a number that are not scale factors are ignored,
and letters immediately following a scale factor are ignored. Hence, 10, 10V,
10VOLTS, and 10HZ all represent the same number, and M, MA, MSEC, and
MMHOS all represent the same scale factor. Note that 1000, 1000.0, 1000HZ,
1E3, 1.0E3, 1KHZ, and 1K all represent the same number.

Chapter 1 1-17


1.5 Output File
The DWS outputs are stored in the file filename.g which has the following
structure:

FILE_NAME
NUMBER_OF_WAVEFORMS
NUMBER_OF_SAMPLES_PER_WAVEFORM
SAMPLING_TIMESTEP
<START_TIME>
WAVEFORM_NAME #1
LIST_OF_SAMPLES
.
.
.
WAVEFORM_NAME #N
LIST_OF_SAMPLES
<COMMENTS>

where:

FILE_NAME is the name of the file containing the simulated waveform(s)
(filename.g).

NUMBER_OF_WAVEFORMS is the number of waveforms included in the
file specified by FILE_NAME. NUMBER_OF_WAVEFORMS is a nonzero
unsigned integer.

NUMBER_OF_SAMPLES is the number of samples of each waveform
included in the file specified by FILE_NAME. NUMBER_OF_SAMPLES is the
same for each waveform belonging to this file.

SAMPLING_TIMESTEP is the time between two contiguous samples of each
stored waveform expressed in seconds. The samples are stored at fixed time step.
SAMPLING_TIMESTEP applies to all the waveforms included in the file and
depends on the TSTEP and LIMPTS values specified within the .TRAN

Chapter 1 1-18


statement of DWS. If LIMPTS is greater than (TSTOP-TSTART)/TSTEP, the
number of stored samples per waveform is limited to (TSTOP-TSTART)/TSTEP
and SAMPLING_TIMESTEP is equal to TSTEP.
If LIMPTS is smaller than (TSTOP-TSTART)/TSTEP, the stored output samples
are obtained by linear interpolation of the simulated values and
SAMPLING_TIMESTEP is equal to (TSTOP-TSTART)/LIMPTS. If LIMPTS is
omitted, SAMPLING_TIMESTEP is equal to TSTEP.
Usually the time is assumed as independent variable and all the waveforms are
given versus time. When necessary, sampling time step can be used with the
meaning of sample identifier. In this last case one of the waveforms can be
assumed as independent variable.

START_TIME is the time expressed in seconds at which DWS begins to save
the results of the simulation and applies to all the waveforms included in the
same file. START_TIME corresponds to TSTART specified within the .TRAN
statement. If START_TIME is not specified, it is assumed to be 0.

WAVEFORM_NAME is the identifier of the waveform specifying the variable
type (voltage, current, etc.) and the node or port (element and node) identifier to
which the waveform is related. The following WAVEFORM_NAME types are
available:

V(N) : voltage at node (port) N referenced to ground (node 0)
V(N1,N2) : voltage at node (port) N1 referenced to node (port) N2
I(ELEM,N) : input current at port N of element ELEM
P(ELEM,N) : instantaneous input power at port N of element ELEM
A(ELEM,N) : incident voltage wave at port N of element ELEM
B(ELEM,N) : reflected voltage wave at port N of element ELEM
Y(ELEM,N) : reference admittance of port N of element ELEM
Z(ELEM,N) : reference impedance of port N of element ELEM
(Z=1/Y)
Q(ELEM,N) : incident instantaneous power at port N of element ELEM
R(ELEM,N) : reflected instantaneous power at port N of element
ELEM
G(ELEM,N) : B/A wave ratio at port N of element ELEM

where the node/element identifiers are those specified in .TRAN statement.

Chapter 1 1-19


LIST_OF_SAMPLE is the list of samples of the waveform specified by
WAVEFORM_NAME. Each sample is given in exponential notation.

The user can add COMMENT in the DWS's output file after the last list of
samples. Each comment line must have an asterisk "*" as first character of the
line.

The DWS's output file format can be also used to describe directly the behavior
of independent sources, the dynamic transfer function of controlled elements and
scattering-parameter elements.

Chapter 1 1-20


1.6 Report File
The report file obtained with the -r option of DWS command is a summary of the
most important features of the simulation including:

- SIMULATION PARAMETERS specified by the user including temperature,
simulation time step and time window.

- NETWORK ELEMENT SUMMARY which classifies the expanded network
derived from the DWS input netlist. For each element type the number of
elements contained in the flattened input netlist (filename.t2) is reported
giving also the total number of elements (En.) and the total number of nodes
(Nn.). The sum of En and Nn is assumed to be an index of the complexity of
the network.

- OUTPUT VARIABLE SUMMARY. that lists all output waveforms (node
voltages, branch currents, waves at the element's ports, instantaneous powers,
etc.) specified in the .TRAN statement and saved in the graphic output file
(filename.g). The number of stored samples per waveform is also specified.

- SIMULATION STATISTICS SUMMARY. giving some figures related to
the complexity. of the simulation to be carried out. This complexity is
evaluated by means of a Complexity Factor (Cf.) defined as the product of
Network Complexity and the number of Calculated Time-Points.

- JOB STATISTICS SUMMARY giving the actual CPU time required for the
simulation run and shared into user and system components. DWS's execution
time is roughly proportional to the Complexity Factor multiplied by the
Specific Elapsed Time (SET.). The SET is defined as the ratio between the
actual Elapsed Time and Cf. SET only depends on the mix of elements
contained in the network and on the computer's power so that simulation time
growth is strictly linear versus the complexity of the network.

Chapter 1 1-21


1.7 Starting DWS
.
Before starting, make sure to have a user-account set up to run DWS. To start
DWS, enter the command:

DWS [-rs] filename

where the options and the arguments have the following meaning:

filename: name of the file containing the source netlist (max allowed length:
100 characters).
-r (report):. information related to running simulation, including circuit
statistics (number and type of elements/nodes of the circuit) and
execution times, is saved in a report file filename.r
-s (silent)..: no output message about the running simulation is issued (useful
in batch mode).

Chapter 1 1-22


Passive Elements DWS

Chapter 2
Passive Elements.
2. 2

2.1 Linear Resistors

2.2 Piece-Wise Linear Resistors

2.3 Time-Controlled Linear Resistors

2.3.1 DC Resistor Function

2.3.2 Pulse Resistor Function

2.3.3 PulsePoly Resistor Function

2.3.4 PulseErfc Resistor Function

2.3.5 Erfc Resistor Function

2.3.6 Delta Resistor Function

2.3.7 Sinusoidal Resistor Function

2.3.8 Piece-Wise Linear Resistor Function

2.3.9 PulsePwl Resistor Function

2.3.10 File Resistor Function

2.3.11 PulseFile Resistor Function

2.4 Voltage-Controlled Resistors

Chapter 2 2-1


2.5 Current-Controlled Resistors

2.6 Static Transfer Function for Voltage or Current Controlled Resistors

2.6.1 Linear Static Transfer Function

2.6.2 Piece-Wise Linear Static Transfer Function

2.6.3 File Static Transfer Function

2.6.4 Threshold Static Transfer Function

2.6.5 Hysteresis Static Transfer Function

2.7 Dynamic Transfer Function for Voltage or Current Controlled Resistors

2.7.1 Unit-step Dynamic Response

2.7.2 S-plane Dynamic Transfer Function

2.7.3 Z-plane Dynamic Transfer Function

2.8 Linear Capacitors

2.9 Linear Inductors

2.10 Unbalanced Transmission Lines

2.11 Balanced Transmission Lines

2.12 Unit-Delay Transmission Lines

2.13 Ideal Transformers

2.14 Junction Diodes

Chapter 2 2-2


2.1 Linear Resistors
.

N1 N2

General form:

RXXXXXXX N1 N2 value

Examples:

R1 1 0 1K
RS 15 22 50

N1 and N2 are the two element nodes. Value is the resistance (in ohms) and may be
positive (1/GMAX  value  1/GMIN) or negative (-1/GMIN  value  -
1/GMAX). If the parameter value is set to zero, the default value 1/GMAX will be
assumed (see the .OPTIONS statement).

Chapter 2 2-3


2.2 Piece-Wise Linear Resistors
..

N+ N-

General form:

PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>>
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> Z0=value
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> C=value
PXXXXXXX N+ N- V1 I1 V2 I2 <V3 I3 ... <V200 I200>> L=value

Examples:

P1 1 0 -1 -.01 0 0 1 .1 Z0=50
PRDR 10 20 0 0 .6 6UA .8 .5MA .85 2.5MA .9 10MA

N+ and N- are the positive and negative element nodes, respectively. The
nonlinear resistance. is described by pairs of values Vi,Ii (Fig.2.2.1). The number
of pairs (n) must be 2 n 200. For V < V1 the resistance keeps the value related
to V1 < V < V2. For V > Vn the resistance keeps the value related to Vn-1 < V <
Vn. The pairs must be written in order of increasing voltage values (Vi  Vi+1).

I
4 (V ,I )
4 4
3
I N+ N- (V ,I )
3 3
2 V
V (V
1
,I )
1
(V ,I )
1 2 2

Fig.2.2.1 Voltage-current relationship for a 2-port PWL resistor.

If the optional parameters Z0, C or L are not given, the reference impedance at
the N+ and N- ports will automatically be set by the circuit elements connected
to the Piece-Wise Linear Resistor. If, due to network topology, the port reference
impedance cannot be defined, one of the three optional parameters must be

Chapter 2 2-4


specified. In this way an additional transmission line with a delay of TSTEP/2,
connected at the intrinsic Piece-Wise Linear Resistor, decouples it from the other
elements of the network.

N+ N+
L/2

Z0
intrinsic
PWL resistor
N+ C
N-
TD=TSTEP/2

L/2
N- N-
Fig.2.2.2: Electrical equivalents of two-port PWL resistor when additional
parameters Z0, C, L are specified for decoupling..

The characteristic impedance of this line may be expressed in one of three forms:
directly as impedance Z0 (ohms), as capacitance C (Farads), so Z0 is set to
TSTEP/(2*C), or as inductance L (Henries), so Z0 is set to 2*L/TSTEP. If the
Piece-Wise Linear Resistor is described as two-port element (i.e. neither N+ nor
N- is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.2.2); if the Piece-Wise Linear Resistor is
described as one-port element (i.e. either N+ or N- is ground node), the
additional line is a true or capacitive or inductive unbalanced transmission line
(Fig.2.2.3).
An alternative method is to use a Unit-Delay Transmission Line for decoupling.
purposes, but in this case an additional line with a delay of TSTEP is introduced
in the network, leading to a transient effect greater than that due to the internal
Z0 setting.
N N
Z0
N L
TSTEP
TD =
2
C
intrinsic
PWL resistor

Fig.2.2.3: Electrical equivalents of one-port PWL resistor when additional
parameters Z0, C, L are specified for decoupling.

Chapter 2 2-5


2.3 Time-Controlled Linear Resistors
.

N1 N2

t

General form:

RXXXXXXX N1 N2 rsource
RXXXXXXX N1 N2 rsource Z0=value
RXXXXXXX N1 N2 rsource C=value
RXXXXXXX N1 N2 rsource L=value

N1 and N2 are the two element nodes. rsource is the time-controlled resistor
function. Resistance value may be positive or negative, but not zero. If positive
resistance value becomes < 1/GMAX, the default value 1/GMAX will be
automatically set; if negative resistance value becomes > -1/GMAX, the
default value -1/GMAX will be automatically set (see the .OPTIONS statement).

Eleven control functions are available: DC, Pulse, PulsePoly, PulseErfc, Erfc,
Delta, Sinusoidal, Piece-Wise Linear, PulsePwl, File and PulseFile. The Pulse,
Piece-Wise Linear and Sinusoidal functions have the same syntax and meaning
of corresponding functions used in SPICE for time-dependent sources. The
PulsePoly, PulseErfc, PulsePwl, PulseFile functions are extensions of the Pulse
function where the behavior of pulse edges can be expressed in several ways
including polynomial, piece-wise linear and generic behaviors described in a
DWS output file.

If one of the three optional parameters Z0, C or L is specified, an additional
transmission line with a delay of TSTEP/2, connected at the intrinsic Time-
Controlled Linear Resistor, decouples it from the other elements of the network.
In this way, if delay-free circuit elements are connected to the Time-Controlled
Linear Resistor, the reference impedance at their ports doesn't have to be
calculated at each simulation step, speeding up the run time.

Chapter 2 2-6


N1 N1
L/2

Z0
intrinsic N1
TCL resistor C
N2
TD=TSTEP/2

L/2
N2 N2
Fig.2.3.1: Electrical equivalents of two-port TCL resistor when additional

Time-Controlled Linear Resistor is described as two-port element (i.e. neither N1
nor N2 is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.3.1); if the Time-Controlled Linear Resistor is
described as one-port element (i.e. either N1 or N2 is ground node), the
(Fig.2.3.2).
Z0 setting.
N N
Z0
N L
TSTEP
TD =
2
C
intrinsic
TCL resistor

Fig.2.3.2: Electrical equivalents of one-port TCL resistor when additional

User note:
Time-Controlled Linear Resistors can be utilized to implement time-dependent
switches. Their use doesn't cause any numerical problem to DWS if Time-
Controlled Linear Resistors are not connected to Delay-Free Loops (DFLs). This
connection could cause problems in particular situations, especially if the

Chapter 2 2-7


dynamic range of resistance values is very large. In these cases (automatically
identified by DWS) the user can decouple the Time-Controlled Linear Resistor
from DFL defining the reference impedance in the element's statement or cut the
DFL by means of additional Unit-Delay Transmission Lines inserted in the
network.

Chapter 2 2-8


2.3.1 DC Resistor Function
.
Syntax: DC <(>RDC<)>

RDC

t

Example:

RIN 4 0 DC( 50 )

The resistor value is time-invariant. The value may optionally be enclosed by
round brackets. The previous statement is completely equivalent to :

RIN 4 0 50

Chapter 2 2-9


2.3.2 Pulse Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> )

R2

R1
0
TD TR PW TF t
PER

Example:
RIN 4 0 PULSE( 1E6 1E-6 5NS 1NS 1NS 24NS 50NS )

parameters default values units

R1 (initial value) ohms
R2 (pulsed value) ohms
TD (delay time) 0.0 seconds
TR (rise time) TSTEP seconds
TF (fall time) TSTEP seconds
PW (pulse width) TSTOP seconds
PER(period) TSTOP seconds

A single pulse so specified is described by the following breakpoint table:

time value

0 R1
TD R1
TD+TR R2
TD+TR+PW R2
TD+TR+PW+TF R1
TSTOP R1

Intermediate points are determined by linear interpolation.

Chapter 2 2-10


2.3.3 PulsePoly Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> )
POLY( C0 C1 C2 C3 C4 C5 C6 )

R2

R1
0
TD TR PW TF t
PER

Example:
RIN 4 0 PULSE( 1E6 1E-6 5NS 1NS 1NS 24NS 50NS )
POLY( 0 .13 -.3.24 23.45 -36.62 21.17 -3.89 )

This function is an extension of the basic Pulse function, when rise and fall edge
behaviors are not linear but can be fitted by a higher-degree polynomial.
The meaning and the default values of PulsePoly parameters are like those of the
corresponding parameters of Pulse, unless edge shape is described by a 6-degree
polynomial in PulsePoly source. C0, C1, ... C6 are the coefficients of the
polynomial. The polynomial is defined between 0 and 1 and, at the lower and
upper limits of this range, must assume the values 0 and 1 respectively in order
that the actual edge shape will reflect the polynomial shape. The polynomial
definition window will be automatically scaled to the actual windows TR, R1, R2,
and TF, R2, R1 (fig.2.3.3.1).

1 6
P OLY(t) 
P OLY(t)= Cn t n
n=0
0 6
0 t 1
BASIC P OLY DEFINITION WINDOW  Cn =1
n=0

R2 R2

R1 R1
TR TF
RISE-EDGE WINDOW FALL-EDGE WINDOW
Fig.2.3.3.1: Mapping of basic poly definition window into rise and fall windows.

Chapter 2 2-11


2.3.4 PulseErfc Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> ) ERFC

R2

R1
0
TD TR PW TF t
PER

Example:

RIN 4 0 PULSE(1E6 1E-6 5NS 1NS 1NS 24NS 50NS ) ERFC

This function is an extension of the basic Pulse function when rise and fall edges
can be fitted by a complementary error function (erfc) behavior. The meaning
and the default values of PulseErfc parameters are like those of the
corresponding parameters of Pulse, unless edge shape is that of erfc. The
definition window of erfc will be automatically scaled to the rise and fall edge
windows (fig.2.3.4.1).

1

erfc
0
0 t 1
BASIC ERFC DEFINITION WINDOW

R2 R2

R1 R1
TR TF
RISE-EDGE WINDOW FALL-EDGE WINDOW

Fig.2.3.4.1: Mapping of basic erfc definition window into rise and fall windows.

Chapter 2 2-12


2.3.5 Erfc Resistor Function
.
Syntax: ERFC( R1 R2 TD TR )

R2

R1
0
TD TR t

Example:

RIN 4 0 ERFC(1E6 1E-6 5NS 1NS )

parameters units

R1 (initial value) ohms
R2 (final value) ohms
TD (delay time) seconds
TR (rise time) seconds

The shape of the waveform is described by the following table:

time value

0 to TD R1
TD+TR to TSTOP R2

from TD to TD+TR the edge shape is like the shape of erfc function.

Chapter 2 2-13


2.3.6 Delta Resistor Function
.
Syntax: DELTA( <R <TD>> )

R

0
TD t

Example:

RIN 4 0 DELTA( 1E6 5NS )


R (impulse value) 1 ohms
TD (delay time) 0.0 seconds

This function implements a delayed Dirac's pulse behavior in according to the
following table.

time value

0 to TD- 0
TD R
TD+ to TSTOP 0

Chapter 2 2-14


2.3.7 Sinusoidal Resistor Function
.
Syntax: SIN( RO RA <FREQ <TD <THETA>>> )

THETA
RA

R0

0
TD t
1/ FREQ
Example:

RIN 4 0 SIN( 1E3 1E3 100MEG 5NS 10MEG )


RO (offset) ohms
RA (amplitude) ohms
FREQ (frequency) 1/TSTOP Hz
TD (delay) 0.0 seconds
THETA (damping factor) 0.0 1/seconds

This function implements an exponentially decaying sinusoidal behavior
described by the following table:

time value

0 to TD R0
TD to TSTOP RO + RA*exp(-(t-TD)*THETA)*sin(2*FREQ*(t-TD))

The syntax is derived from SPICE sinusoidal source.

Chapter 2 2-15


2.3.8 Piece-Wise Linear Resistor Function
.
Syntax: PWL( T1 R1 T2 R2 <T3 R3 <T4 R4 ... <T199 R199
<T200 R200>>>> )

R2
R3

R1 R4 R5

0
T1 T2 T3 T4 T5 t
Example:

RIN 4 0 PWL( 10NS 1E6 11NS 1E-6 15NS 1E-6 16NS 1E6 )

This function implements a piece-wise linear behavior containing up to 200
breakpoints. Each breakpoint is defined by a pair of values (Ti, Ri) that specifies
the resistance Ri (in ohms) of the time-controlled resistor at time=Ti (in
seconds). The number of pairs (n) must be 2 n 200. The value of the
resistance at intermediate values of time is determined by using linear
interpolation on the input values. For time < T1 the value of the resistance is R1,
for time > Tn the value of the resistance is Rn. The pairs must be written in order
of increasing time values (Ti  Ti+1), otherwise a specific error message is
issued on the standard output.

Chapter 2 2-16


2.3.9 PulsePwl Resistor Function
.
Syntax: PULSE( R1 R2 <TD <TR <TF <PW <PER>>>>> ) PWL( T1 Y1
T2 Y2 <T3 Y3 <T4 Y4 ... <T199 Y199 <T200 Y200>>>> )

Yn

R2

Y2 Y3
Y4
R1 Y5
0 t Y1
TD TR PW TF
PER T1 T2 T3 T4 T5 Tn t

Example:

RIN 4 0 PULSE(1E6 1E-6 5NS 2NS 2NS 23NS 50NS ) PWL( 0 1E6
.3NS 1E3 .6NS 100 1NS 10 1.4NS 1E-2 2NS 1E-6 )

can be fitted by a piece-wise linear behavior. The meaning and the default values
of PulsePwl parameters are like those of the corresponding parameters of Pulse,
unless edge shape is described by the pairs of values Ti, Yi in PulsePwl resistor.
The pairs, written in order of increasing time values (Ti  Ti+1), determine edge
shape, while the actual value of the resistance is defined by the parameters R1,
R2, TR, TF. The PWL definition window will be automatically scaled to the
actual rise and fall edge windows. The piece-wise linear swing Yn - Y1 (n:
number of pairs) will become the pulse swing R2 - R1, the time interval Tn - T1
will become TR for the rise edge and TF for the fall edge as explained in
section 2.3.4.

Chapter 2 2-17


2.3.10 File Resistor Function
.
Syntax: FILE( filename )

R2
R3

R1 Rn
R0

0 T 2T 3T nT t

Example:

RIN 4 0 FILE(ressamples )

This function implements a time-controlled resistor whose behavior is described
by a DWS-format file identified by the parameter filename. In this file a
sampling timestep (T) will be specified. If the simulation timestep (TSTEP in
.TRAN statement) is not coincident with the file timestep, the resistance values
will be determined using linear interpolation of the values contained in the file.
After the last sample contained in the file, the resistance value is assumed to be
equal to the value of the last sample. File name must begin with a letter. Strings
beginning with 'DC' or 'dc' are invalid file names since these strings are
interpreted as the DC parameter of an independent source.

Chapter 2 2-18


2.3.11 PulseFile Resistor Function
.
Syntax: PULSE( NC NC <TD <NC <NC <PW <PER>>>>> )
FILE(filename)

Yn

Y1 Y2

0 t Y0
TD PW
PER 0 T 2T n*T t

Example:

RIN 4 0 PULSE( 0 0 5NS 0 0 23NS 50NS ) FILE(ressamples )

can be described by a behavior contained in a DWS-format file identified by the
parameter filename. File name must begin with a letter. Strings beginning with
'DC' or 'dc' are invalid file names.
The meaning and the default values of the parameters TD, PW and PER are like
those of the corresponding parameters of Pulse, whereas initial value, pulsed
value, rise time, fall time and edge shape are determined by resistance samples
versus time contained in the file. For this reason the initial, pulsed, rise time and
fall time values specified in the PULSE syntax will be not considered.

parameter value

R1 Y0 (1st file sample)
R2 Yn (last file sample)
TR n*T
TF n*T

Chapter 2 2-19


If the simulation timestep (TSTEP in .TRAN statement) is not coincident with
the file timestep, the resistance values will be determined using linear
interpolation of the values contained in the file.

Chapter 2 2-20


2.4 Voltage-Controlled Resistors
.

Control Link Chain
N1
DELAY

NC+ D.T.F. VCR
S.T.F.
-
Dynamic Static
Transfer Transfer N2
NC- Function Function

General form

RXXXXXXX N1 N2 NC+ NC- STATIC-TRANSFER-FUNCTION
<DYNAMIC-TRANSFER-FUNCTION> <TD>
<DYNAMIC-TRANSFER-FUNCTION> <TD> Z0=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> C=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> L=value

Control Link Chain
N1
DELAY

NC+ S.T.F. D.T.F. VCR

-
Static Dynamic
NC- Function Function

General form

RXXXXXXX N1 N2 NC+ NC- <DYNAMIC-TRANSFER-FUNCTION>
STATIC-TRANSFER-FUNCTION <TD>
STATIC-TRANSFER-FUNCTION <TD> Z0=value

Chapter 2 2-21


STATIC-TRANSFER-FUNCTION <TD> C=value
STATIC-TRANSFER-FUNCTION <TD> L=value

This form is an extension of the syntax used in SPICE for voltage-controlled
sources. N1 and N2 are the two element nodes. NC+ and NC- are the
positive and negative controlling nodes, respectively. The controlling signal is
V(NC+) - V(NC-). Like the other voltage and current controlled elements, the
Voltage-Controlled Resistors can have two types of control link chain with
different positions of the transfer functions. The static transfer function must be
specified, while the dynamic transfer function is optional.
The optional parameter TD is a delay time expressed in seconds. The Delay
operator is the first block of the control link chain and acts on the controlling
signal. The minimum delay is corresponding to TSTEP (specified in the .TRAN
statement) even if the input parameter TD is omitted or set to a value < TSTEP.
This approximation can be considered when zero-delay control links are
simulated. Regarding the delay discretization process, both ROUNDING and
INTERPOLATION methods described in 1.2.5 are allowed depending on the
DELAYMETH option set by the user on the DWS input file.
Resistance value may be positive or negative, but not zero. If positive resistance
value becomes < 1/GMAX, the default value 1/GMAX will be automatically set;
if negative resistance value becomes > -1/GMAX, the default value -1/GMAX
will be automatically set (see the .OPTIONS statement).

If one of the three optional parameters Z0, C or L is specified, an additional
transmission line with a delay of TSTEP/2, connected at the intrinsic Voltage-
Controlled Resistor, decouples it from the other elements of the network. In this
way, if delay-free circuit elements are connected to the Voltage-Controlled
Resistor, the reference impedance at their ports doesn't have to be calculated at
each simulation step, speeding up the run time.

Chapter 2 2-22


N1 N1
intrinsic L/2
VCR
Z0
NC+ N1 NC+ NC+
C
NC- N2 NC- NC-
TD=TSTEP/2

L/2
N2 N2

Fig.2.4.1: Electrical equivalents of two-port VCR when additional parameters
Z0, C, L are specified for decoupling.

Voltage-Controlled Resistor is described as two-port element (i.e. neither N1 nor
N2 is ground node), the additional line is a true or capacitive or inductive
balanced transmission line (Fig.2.4.1); if the Voltage-Controlled Resistor is
described as one-port element (i.e. either N1 or N2 is ground node), the
(Fig.2.4.2).
Z0 setting.

N N
Z0
N L
TSTEP
TD =
2
NC+ NC+ NC+
C
NC- intrinsic NC-
NC-
VCR

Fig.2.4.2: Electrical equivalents of one-port VCR when additional

Use note:
the Voltage-Controlled Resistors (VCR) can be utilized to implement controlled
switches that in turn can model logic functionality. The use of VCR doesn't cause

Chapter 2 2-23


any numerical problem to DWS if VCRs are not connected to Delay-Free Loops
(DFLs). This connection could cause some solution problems in particular
situations especially if the dynamic range of resistance values is very large. In
these cases (automatically identified by DWS) the user can decouple the VCR
from DFL defining the reference impedance in the element's statement or cut the
DFL by means of additional Unit-Delay Transmission Lines inserted in the
network.

Chapter 2 2-24


2.5 Current-Controlled Resistors
.

Control Link Chain
NC N1
DELAY
I
D.T.F. CCR
S.T.F.
ELEM
Dynamic Static
Function Function

General form:

RXXXXXXX N1 N2 I(ELEM,NC) STATIC-TRANSFER-FUNCTION
<DYNAMIC-TRANSFER-FUNCTION> <TD>
<DYNAMIC-TRANSFER-FUNCTION> <TD> Z0=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> C=value
<DYNAMIC-TRANSFER-FUNCTION> <TD> L=value

Control Link Chain
NC N1
DELAY
I
D.T.F. CCR
S.T.F.
ELEM
Static Dynamic
Function Function

General form:

RXXXXXXX N1 N2 I(ELEM,NC) <DYNAMIC-TRANSFER-FUNCTION>
STATIC-TRANSFER-FUNCTION <TD>

Chapter 2 2-25

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