3. TTrraannssiissttoorr SSiizzee SSccaalliinngg
MOSFET performance
improves as size is
decreased:
shorter switching time,
lower power
consumption.
2 orders of magnitude reduction in transistor size in 30 years.
4. SSiiggnniiffiiccaanntt BBrreeaakktthhrroouugghhss
Transistor size: Intel’s research labs have recently shown the world’s smallest
transistor, with a gate length of 15nm. We continue to build smaller and smaller
transistors that are faster and faster. We've reduced the size from 70 nanometer to 30
nanometer to 20 nanometer, and now to 15 nanometer gates.
Manufacturing process: A new manufacturing process called 130 nanometer process
technology (a nanometer is a billionth of a meter) allows Intel today to manufacture
chips with circuitry so small it would take almost 1,000 of these wires placed side-by-
side to equal the width of a human hair. This new 130-nanometer process has
60nm gate-length transistors and six layers of copper interconnect. This process is
producing microprocessors today with millions of transistors and running at multi-gigahertz
clock speeds.
Wafer size: Wafers, which are round polished disks made of silicon, provide the base
on which chips are manufactured. Use a bigger wafer and you can reduce
manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches)
diameter silicon wafer size, up from the previous wafer size of 200mm (about 8
inches).
14. RReeccuurrrriinngg CCoossttss
v a rr i aabbllee ccoosstt == ccoosstt ooff ddiiee ++ ccoosstt ooff ddiiee tteesstt ++ ccoosstt ooff ppaacckkaaggiinngg --------------------------------------------------------------------------------------------------------------------------------
ffiinnaall tteesstt yyiieelldd
ccoosstt ooff ddiiee == ----------- - --cc--o-o---ss--tt-- --oo--ff-- --ww----aa--f-e-e---rr-------------------------- ddiieess ppeerr wwaaffeerr ×× ddiiee yyiieelldd
d i e s pp ee r ww aa f ee rr == -- p---- --××--- - ((--ww----a-a---ff--ee--rr-- --dd--ii--aa---m-m----ee--tt--ee--rr--//--22----))--22- - -- -- - -- - p ×× wwaaffeerr ddiiaammeetteerr - -- -- - -- -- - -- -- - -- -- - -- -- - -- -- - -- -- - -- -- - dd----iiee aarreeaa Ö 22 ×× ddiiee aarreeaa
ddiiee yyiieelldd == ((11 ++ ((ddeeffeeccttss ppeerr uunniitt aarreeaa ×× ddiiee aarreeaa))//a))--a
15. YYiieelldd EExxaammppllee
Example
wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
a = 3 (measure of manufacturing process complexity)
252 dies/wafer (remember, wafers round dies square)
die yield of 16%
252 x 16% = only 40 dies/wafer die yield !
Die cost is strong function of die area
proportional to the third or fourth power of the die area
Staffing costs computed at $150K/staff year (in 1997 dollars)
While the cost of producing a single transistor has dropped exponentially over the past few decades, the basic cost equation hasn’t changed.
Cost of a circuit is dependent upon the chip area.
Alpha depends upon the complexity of the manufacturing process (and is roughly proportional to the number of masks). A good estimate for today’s complex CMOS process is alpha = 3.
Defects per unit area is a measure of the material and process-induced faults. A value between 0.5 and 1 defects/cm**2 is typical today but strongly depends upon the maturity of the process.
While the cost of producing a single transistor has dropped exponentially over the past few decades, the basic cost equation hasn’t changed.
Cost of a circuit is dependent upon the chip area.
Alpha depends upon the complexity of the manufacturing process (and is roughly proportional to the number of masks). A good estimate for today’s complex CMOS process is alpha = 3.
Defects per unit area is a measure of the material and process-induced faults. A value between 0.5 and 1 defects/cm**2 is typical today but strongly depends upon the maturity of the process.