How much longer will we be able to rely on planar scaling to deliver Moore's Law? And what then?

1. 1v0
Prof. Ian Phillips
Principal Staff Eng’r,
ARM Ltd
ian.phillips@arm.com
Visiting Prof. at ...
y p
Many-Core Workshop
NEC, Birmingham
Contribution to Industry
19mar12
Award 2008
The closer you are to death;
the more you realize you are alive.
The closer you are to death;
the harder you cling to life.
Top 5000 J.Simpson, Touching the Void, 1985
1

2. Moore’s Law: c1965
 “Moore's Law” was coined by Carver Mead in 1970, from Gordon
Moore's article in Electronics Magazine 19 April 1965 "Cramming more
components onto integrated circuits .
circuits“
“The complexity for minimum
p y
component costs has increased at a rate
of roughly a factor of two per year ...
Certainly over the short term this rate can be
expected to continue, if not to increase. Over
t dt ti tt i O
the longer term, the rate of increase is a bit
more uncertain, although there is no reason to
believe it will not remain nearly constant for at
y f
least 10 years. That means by 1975, the number
of components per integrated circuit for
minimum cost will be 65,000. I believe that such
allarge circuit can be built on a single wafer”
i it b b ilt i l f ”
Gordon Moore, Founder of Intel
In 1965 he was designing ICs with ~50 transistors!
g g
Moore’s Law has held for ~50 years ... Taking us to 100B transistor ICs
2

3. Approximate Process Geometry
y
3
1um
10um
10nm
100nm
100um
Transistors
s/Chip (M)
Moore’s Law ...
X
ITRS’99
Transistor
r/PM (K)

4. All Exponentials Have Got to End ...
130nm
90nm
30nm
14nm
14
7nm
4

5. All Exponentials Have Got to End ...
 Growing opinion that 14 or 7nm will be the
130nm smallest yieldable node (any process).
90nm
 Just 3-4 gen. (5-8yr) to the
end of Planar Scaling
30nm  Only things on
O l thi
the drawing
board today ...
14nm
14
... can get into the
last of the of planar chips! 7nm
 Its the end-of-the-road for
‘promising technologies’ !
 Clean-Sheet Synthesis
 Scalable Processor Arrays
 Formal Design
...The future lies with Hybrid,
 Top-Down Design Evolutionary Architectures
5

6. Approximate Process Geometry
y
6
1um
10um
10nm
100um
Transistors
s/Chip (M)
100nm
Moore’s Law ...
X
ITRS’99
Transistor
r/PM (K)

7. What Happened to the Productivity Gaps?
Reuse Happened !
 <1995 chip design was entire ...
 Moore’s Law was handled by Bigger Teams and Faster Tools
 With Improved Productivity through HDL and Synthesis
 >1995 reuse quietly entered the picture ...
 Circuit Blocks
 CPUs (and Software) ... With
 External IP Supporting
Methodology!
 Up-Integration
(Incl. Software)
 Chip Reuse (ASSP)
... Delivering Productivity Quality and Reliability
Productivity,
... Birth of HW/SW IP Companies (eg ARM)
... But brought Architectural Chaos & Commoditisation of FABs
7

8. Products Make Money
 21c Businesses have to be
 Selling things that People (End-Customers) want to buy.
 Operations and Competition is Global and so are Investors
 Nationality has little meaning
 Business needs
 End-Customers buy Functionality not Technology
 Technologies enable Product Options
 Business-Models make Money
 New Products are
 Design is a Cost/Risk to be Minimised
 T h l
Technology (HW SW, Mechanics, O ti
(HW, SW M h i Optics, etc)
t )
is (just) a means to a Product end!
 New Technology increases Cost/Risk ... But not always Value
... Globalisation makes Business Focus on their Core-Competence!
8

9. Architecting an iConic Many-Core Product ...
9

10. It’s Not Solid Obsidian !?!
Down 1-Level:
Modules
The Control Board.
10 Source ... http://www.ifixit.com

11. The Control Board (A-side)
Down 2-Levels: Sub-Assemblies
 Visible Design-Team Members ...
 Samsung (flash memory) - (ARM Partner)
 Cirrus Logic (audio codec) - (ARM Partner)
g ( ) ( )
 AKM (Magnetic Sensor)
 Texas Instruments (Touch Screen Controller and mobile DDR) - (ARM Partner)
 Invisible Design-Team Members ...
g
 Software Tools, OS & Drivers, GSM Security; Graphics, Video and Sound ...
 Manufacturing, Assembly, Test, Certification ...
11 Source ... http://www.ifixit.com

12. The Control Board (B-side)
Down 2-Levels: Sub-Assemblies
 Visible Design-Team Members...
 A4 PProcessor, specified b A l d i
ifi d by Apple, designed and manufactured b S
d d f t d by Samsung ...
 The central unit that provides the iPhone 4 with its GP computing power.
 Reported to contain ARM A8 600 MHz CPU (other ARM CPUs and IP)
 ST-Micro (3 axis Many Processors & Software
gyroscope) - (ARM Partner)
 Broadcom (Wi-Fi, Bluetooth, and GPS) - (ARM Partner)
..with..
 Skyworks (GSM) and Evolutional Architecture !
Hybrid
 Triquint (GSM PA)
 Infineon (GSM Transceiver) - (ARM Partner)
GPS
Bluetooth,
EDR &FM
12 Source ... http://www.ifixit.com

13. Multicore ARM On-Chip ...
 Heterogeneous Multicore
 Systems have existed for a long time:
Application UI & 3D graphics Power Manager
Mali™-400
Cortex™-A8 MP Cortex-M3
Interconnect
Memory
13

14. Coherent Multicore Cluster
 Homogenous Multicore
 cluster, as part of a heterogeneous system:
User Interface
… and 3D graphics
g p Power Manager
g
Cortex-A9 Cortex-A9
Coherency Logic
Mali-400 MP Cortex-M3
Interconnect
14

15. Multiple Clusters
 Multiple Homogeneous Coherent Clusters
… …
Cortex-A15 Cortex-A15 Cortex-A15 Cortex-A15
Coherency Logic in L2 Cache Coherency Logic in L2 Cache
Coherent Interconnect
15

16. Multi-Processors on a Chip
Users require a pocket ‘Super-Computer’ ...
 Silicon Technology Provides a few-Billion raw transistors ...
 ARM’s IP makes it Practical to utilise them ...
• 10 Programmable Processors
11 Processors• 4 x A9 Processors (2x2):
But the Chip ArchitectureMALI 400 Fragment Proc:
• 4 x is
also Hybrid and Evolutional ! 400 Vertex Proc
• 1 x MALI Proc.
• 1 x MALI Video CoDec
• Software Stacks, OS’s and
Design Tools/
• ARM Technology gives
chip/system designers a
good start. And ...
start
• Improves Productivity
• Improves TTM
• I
Improves Quality/Certainty
Q lit /C t i t
16

17. nVidea Tegra 3 Processor (~1B transistors)
nVidea Tegra3
ARM
ARM
ARM ARM
ARM ARM
17

18. The Apple A4 SIP Package (Cross-section)
Memory
‘Package’
2 Memory Dies
Glue Processor SOC Di
P Die
4-Layer Platform
Package
Package’
IC Packaging
 The processor is the centre rectangle. The silver circles beneath it are solder balls.
 Two rectangles above are RAM die, offset to make room for the wirebonds.
 Putting the RAM close to the p
g processor reduces latency, making RAM faster and cuts p
y, g power.
 Unknown Mfr (Memory)
 Samsung/ARM (Processor)
 Unknown (SIP Technology)
18 Source ... http://www.ifixit.com

19. 3D: Keeping Moore’s Law Going
Many-More Cores
Many More ‘Cores’ ...
Hardware and Software ...
Very-Hybrid Architecture ...
Even-More P
E M Power P bl
Problems ...
19

20. Reliability and Robustness
 As Process Geometry falls; Reliability and Robustness does as well
 Susceptibility to high-energy particles
 Wear-out mechanisms
 Variability
 State depe de cy
State-dependency
 Imperfection in design
 Current 3D techniques are even more vulnerable to defects
 Throw away good chiplets with the bad-ones
 Additional chiplet/chiplet interactions
 Can t
Can’t fully test chiplets before assembly
 Increased assembly loss/imperfections
 Limited re-working potential
 Must break the 100% functionality requirement
 Requires Functional on Imperfect (Design) Platforms
20

21. The Failure of Power Scaling
Node 45nm 22nm 11nm
Year 2008 2014 2020
Area-1 1 4 16
Peak freq 1 1.6
16 2.4
24
Power 1 1 0.6
(4 x 1)-1 = 25% (16 x 0.6)-1 = 10%
Dark Dark
Silicon Silicon
Exploitable Si
(in 45nm power budget)
25% 10%
Source: ITRS 2008 … Severely limits the circuitry we can Turn On !
21

22. Conclusions
 Planar Processing ends in 3-5yrs
 And takes with it all clean-sheet planar design possibilities
 3D takes Moore's Law into its next decade
 Productivity through Reuse is Business Imperative
 ‘Productivity Aids’ without Methods and Legacy Compatibility are Useless
Productivity Aids Useless.
 Multi-Processor Architecture is driven by the System Functionality
 They will always be: Multi-Discipline, Multi-Process, Multi-Geometry,
Multi-Architecture, Multi-Company, Multi-Die and Multi-Chip.
 All Architectures will be Hybrid and Evolutionary
 Power Efficiency is not just a Societal Issue
 We cannot use what we can create without overcoming it (We need x100!)
 Business only needs to be “better” than its competitors
 Good enough; is enough.
 Cannot depend on 100% functionality any more
 Need F nctionalit despite imperfection in Design and Man fact re
Functionality Manufacture
22

23. Multi-Processing: Just a means to an end!
Its the System Stupid 
23