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Donna S. Nielsen
88 Jefferson Ct..
Yorktown Heights
(914)245-8332 (H) (914)588-5130 (C)
znielsen@live.com
_________________________________________________________________________
Professional Experience
Over 30 years of experience in Quality Assurance, Manufacturing, Development and Research in the
microelectronics and semiconductor industry. I have strong technical skill in the area of fabrication, device
characterization, process development, process integration, yield enhancement and quality assurance. I have
demonstrated strong skills in leadership and project management as the manager of engineering organizations
ranging from laboratories to quality organizations. In the last 12 years I have managed technical service
organizations for Research, Development and Integrated Supply Chain/ Supplier Quality Engineering. I have
experience both with the supplier and the customer end of major manufacturing organization. And have the
ability to build strong teams that deliver results.
GLOBALFOUNDRIES, Fab 9/10 Quality (2015 to present)
Hopewell Junction, NY
Sr Manager Supplier Quality Engineering and Material Quality Lab:
Sr. Manager of Supplier Quality Engineering (SQE) and Material Quality Lab (12 people) in support of
200/300mm Manufacturing (2 sites). Execution on supplier quality initiatives like LEAN, Six Sigma, audits,
SCARs, Ship to Control in order to drive supplier quality improvement with the ultimate goal of zero
excursion. Well versed in ISO9001, TS16949, AS9001c compliance. Using customer facing opportunities
and best practices to drive continuous improvements. Additionally managed analytical lab services in
support of SQE material validation.
IBM, Integrated Supply Chain (2010-2015)
Hopewell Junction, NY
Manager of Material Quality Assurance Labs:
Procurement Engineering Manager (10 people) of material quality and assurance labs, supporting 300mm
Fabs and Packaging organizations. Responsible for developing, implementing and sustaining the supply
chain for chemicals and parts for all generations of semiconductors technologies at IBM. Worked with
procurement to achieve a 10% cost take down per year. Proficient in DOX, LEAN and Six Sigma. Working
on Green Belt Certification via IBM program.
IBM, Research Division (2004 to 2010)
Yorktown Heights, NY
Manager Central Scientific Services:
Engineering manager of service organization which supports IBM and external customers by providing proof
of concept structures in the areas of Si and packaging technology. Extensive work on 3Di and Photo Voltaic
projects. Responsibilities include people management (15 people), lab management (4 labs), project
management and finance.
IBM, Microelectronics Division (2000 to 2006)
Hopewell Junction, NY
WB CPI, & Chip Design:
Lead Integrator for 90, 65 & 45nm Wirebond Technology (WB) Chip Package Integration Qualifications
(CPI). Worked extensively with customers, partners, packaging and reliably teams to develop the
technology requirements. Qualified multiple technology solutions on time and with in cost targets.
Back End of Line (BEOL)/Fare Back End of Line (FBEOL) Integration and CPI:
Member of 300mm technology team responsible for qualifying flip chip (C4) solutions for both Ceramic and
Laminate packages for 90nm through 45nm technologies. This required in-depth knowledge of BEOL ILD
deposition, Litho, RIE, wets and CMP. In addition I provided product management support for 45nm SRAM
technology qualification.
C4/FBEOL Development and Integration:
Research and development in the area packaging and of flip chip (C4) development for CMOS at 0.13um to
0.10um ground rules. Responsibilities include unit process development and process integration for a verity
of Lead free chip interconnects solutions.
MOTOROLA, Semiconductor Product Sector (1991 to 2000)
Phoenix AZ.
Senior Process Engineer, Bipolar Manufacturing Complex (BMC): (1999 to 2000)
Responsible for manufacturing support, process development and process integration for Bipolar
Manufacturing Complex. Etch section head for Pressure Sensors, Standard Linear, Smart MOS, MOSAIC I,
RFLDMOS and ADVM devices.
Senior Process Engineer, MEMS1: (1995 to 1999)
Responsible for manufacturing support, process development and process integration for back end
operations (Pressure Sensors and Accelerometers.). Back end operations include Sacrificial Etch and
Release, Wafer to Wafer Glass Frit Bond, Screen Print and Glaze operations. Developed non-destructive void
identification equipment trough use of acoustic scanning microscopy and real time X-ray. Implementation of
SPC on back end processes for QS9000 compliance.
Module Manager, OPTO: (1993 to 1995)
Managed FEOL in the GaAs LED Wafer Fab. Operations: LPE (Liquid Phase Epitaxy), Polish, Diffusion, GaAs
(all operations) and Back-lap. Responsible for both sustaining and project engineering. Responsibilities
include cost reduction through process optimization, new process development, cycle time and scrap
reduction. SPC Engineering Team Leader Opto (chemical thinning with Semitool electronics/OSPD Cleans
Engineering representative at the Motorola Cleans Summit.
Process Engineer, OPTO: (1991 to 1993)
Sustaining engineering for LPE, Polish and Diffusion operations in the GaAs LED Wafer Fab. Responsible for
yields, cycle time and scrap. Also responsible for cost reductions through process optimization and new
process development. This included grid etch elimination, Reliability failure due to aberrant forward voltage
failures(funny Vf) elimination and qualification of new vendor for Ga. Hands on work include the
maintenance of the LPE Furnaces (SEMY) and purchase and installation of new equipment.
MOTOROLA SALES FEDERAL SEGMENT (1990 to 1991)
Maitland, FL.
Federal Segment Sales:
Sales and applications Engineer II. Identify and develop opportunities at key customers in conjunction with
sales. Provide technical training on MOTOROLA technologies and products to customers and sales. Provide
market trends, new products and competitive information to sales, marketing and product groups.
Coordinate major quotes and product specifications with sales.
MARTIN MARIETTA ELECTRONICS & MISSILES GROUP (1986 to 1990)
Orlando, FL
Development Engineer:
Member of the Research, Development & Technologies Group at the Optical Components Center.
Responsible for optical thin film design and fabrication of VIS and IR systems. This includes optical end
environmental testing, fabrication, and assembly. Familiar with a variety of film deposition techniques such
as PVD, RIPD, CVD and sputtering. Involved in the development of state of the art rain erosion and low
observables technology. Developed and constructed BRDF measurement facility and a holographic
inspection station for the diamond turning.
Education
________________________________________________________________________________
SUNNY at Stony Brook Stony Brook, NY (1978 to 1982)
B.S. ENGINEERING CHEMISTRY & BIOCHEMISTRY- Emphasis on physical chemistry and genetic engineering
(Recombinant DNA research and micro biology)
University of Rochester Rochester, NY (1983 to 1985)
M.S. MATERIAL SCIENCE- Emphasis on ceramics and optical materials
University of Central Florida Orlando, FL (1986 to 1990)
M.S. ELECTRICAL ENGINEERING- uncompleted
Courses: Digital circuits, electromagnetic fields, signals & communication, electronic engineering, optics, thin films &
technology.
University of California Los Angeles, CA (1986)
UCLA extension course on optical coating technology given by Phil Baumeister
Organizations & Patents
_______________________________________________________________________________
At various times member of GaAs MANtech, MRS, UGIM, SPIE, OSA, AVS and IEEE, SWE. ASE, PITCON
Patents:
Micro-machined component and method of manufacture ,US Pat. 6811714 Issued 11/2/2004 –Freescale
Improved interface between a I-III-VI2 material layer and a molybdenum substrate, App. Num. EP20100306519 20101227
App. Date 12/27/2010-Nexis
IBM Patent name Patent date Patent number
Patent issuing country or
region
INHIBITION OF TIN OXIDE FORMATION IN LEAD FREE INTERCONNECT FORMATION 2005-05-31 6900142 United States
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION
BARRIER LAYERS
2008-08-12 7410833 United States
STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 2007-12-25 7312529 United States
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION
BARRIER LAYERS
2008-10-03 4195886 Japan
STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 2010-05-11 7714452 United States
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION
BARRIER LAYERS
2010-04-28 ZL200510060057.1 China
METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL
CAP STRUCTURE
2011-01-04 7863183 United States
METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL
CAP STRUCTURE
2011-03-16 ZL200780001812.6 China
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION
BARRIER LAYERS
2011-04-12 7923849 United States
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION
BARRIER LAYERS
2011-09-27 8026613 United States
METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL
CAP STRUCTURE
2013-01-25 5186392 Japan
Papers:
“Finite Amplitude Rotational Surface Tension Instabilities”, Second Annual Mixed Fluids Conference, Casowasco, NY, March
1985.
“Green” Process and productivity Improvements in GaAs light emitting dopdes Wafer Fab, Electronics and the environment;
May 1995.
Optimization of surface Altering processing for GaAs Light emitting diodes, US conference on GaAs Manufacturing TECHnology;
May 1995
MAT’s and ISTFA on “Evaluation and Elimination of Forward Snapback defect in GaAs Light Emitting Diodes”, “Green Process
and Productivity Improvements in GaAs LED Wafer Fab.” IEEE Electronics and the Environment, Orlando, FL, May 1995.
“Excimer laser debridement of necrotic erosions of skin without collateral damage “, Proc. SPIE 8092, 809213 (2011);
doi:10.1117/12.889741

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Donna S. Nielsen Resume_2016

  • 1. Donna S. Nielsen 88 Jefferson Ct.. Yorktown Heights (914)245-8332 (H) (914)588-5130 (C) znielsen@live.com _________________________________________________________________________ Professional Experience Over 30 years of experience in Quality Assurance, Manufacturing, Development and Research in the microelectronics and semiconductor industry. I have strong technical skill in the area of fabrication, device characterization, process development, process integration, yield enhancement and quality assurance. I have demonstrated strong skills in leadership and project management as the manager of engineering organizations ranging from laboratories to quality organizations. In the last 12 years I have managed technical service organizations for Research, Development and Integrated Supply Chain/ Supplier Quality Engineering. I have experience both with the supplier and the customer end of major manufacturing organization. And have the ability to build strong teams that deliver results. GLOBALFOUNDRIES, Fab 9/10 Quality (2015 to present) Hopewell Junction, NY Sr Manager Supplier Quality Engineering and Material Quality Lab: Sr. Manager of Supplier Quality Engineering (SQE) and Material Quality Lab (12 people) in support of 200/300mm Manufacturing (2 sites). Execution on supplier quality initiatives like LEAN, Six Sigma, audits, SCARs, Ship to Control in order to drive supplier quality improvement with the ultimate goal of zero excursion. Well versed in ISO9001, TS16949, AS9001c compliance. Using customer facing opportunities and best practices to drive continuous improvements. Additionally managed analytical lab services in support of SQE material validation. IBM, Integrated Supply Chain (2010-2015) Hopewell Junction, NY Manager of Material Quality Assurance Labs: Procurement Engineering Manager (10 people) of material quality and assurance labs, supporting 300mm Fabs and Packaging organizations. Responsible for developing, implementing and sustaining the supply chain for chemicals and parts for all generations of semiconductors technologies at IBM. Worked with procurement to achieve a 10% cost take down per year. Proficient in DOX, LEAN and Six Sigma. Working on Green Belt Certification via IBM program. IBM, Research Division (2004 to 2010) Yorktown Heights, NY Manager Central Scientific Services: Engineering manager of service organization which supports IBM and external customers by providing proof of concept structures in the areas of Si and packaging technology. Extensive work on 3Di and Photo Voltaic projects. Responsibilities include people management (15 people), lab management (4 labs), project management and finance. IBM, Microelectronics Division (2000 to 2006) Hopewell Junction, NY WB CPI, & Chip Design: Lead Integrator for 90, 65 & 45nm Wirebond Technology (WB) Chip Package Integration Qualifications (CPI). Worked extensively with customers, partners, packaging and reliably teams to develop the technology requirements. Qualified multiple technology solutions on time and with in cost targets. Back End of Line (BEOL)/Fare Back End of Line (FBEOL) Integration and CPI: Member of 300mm technology team responsible for qualifying flip chip (C4) solutions for both Ceramic and Laminate packages for 90nm through 45nm technologies. This required in-depth knowledge of BEOL ILD deposition, Litho, RIE, wets and CMP. In addition I provided product management support for 45nm SRAM technology qualification. C4/FBEOL Development and Integration: Research and development in the area packaging and of flip chip (C4) development for CMOS at 0.13um to 0.10um ground rules. Responsibilities include unit process development and process integration for a verity of Lead free chip interconnects solutions.
  • 2. MOTOROLA, Semiconductor Product Sector (1991 to 2000) Phoenix AZ. Senior Process Engineer, Bipolar Manufacturing Complex (BMC): (1999 to 2000) Responsible for manufacturing support, process development and process integration for Bipolar Manufacturing Complex. Etch section head for Pressure Sensors, Standard Linear, Smart MOS, MOSAIC I, RFLDMOS and ADVM devices. Senior Process Engineer, MEMS1: (1995 to 1999) Responsible for manufacturing support, process development and process integration for back end operations (Pressure Sensors and Accelerometers.). Back end operations include Sacrificial Etch and Release, Wafer to Wafer Glass Frit Bond, Screen Print and Glaze operations. Developed non-destructive void identification equipment trough use of acoustic scanning microscopy and real time X-ray. Implementation of SPC on back end processes for QS9000 compliance. Module Manager, OPTO: (1993 to 1995) Managed FEOL in the GaAs LED Wafer Fab. Operations: LPE (Liquid Phase Epitaxy), Polish, Diffusion, GaAs (all operations) and Back-lap. Responsible for both sustaining and project engineering. Responsibilities include cost reduction through process optimization, new process development, cycle time and scrap reduction. SPC Engineering Team Leader Opto (chemical thinning with Semitool electronics/OSPD Cleans Engineering representative at the Motorola Cleans Summit. Process Engineer, OPTO: (1991 to 1993) Sustaining engineering for LPE, Polish and Diffusion operations in the GaAs LED Wafer Fab. Responsible for yields, cycle time and scrap. Also responsible for cost reductions through process optimization and new process development. This included grid etch elimination, Reliability failure due to aberrant forward voltage failures(funny Vf) elimination and qualification of new vendor for Ga. Hands on work include the maintenance of the LPE Furnaces (SEMY) and purchase and installation of new equipment. MOTOROLA SALES FEDERAL SEGMENT (1990 to 1991) Maitland, FL. Federal Segment Sales: Sales and applications Engineer II. Identify and develop opportunities at key customers in conjunction with sales. Provide technical training on MOTOROLA technologies and products to customers and sales. Provide market trends, new products and competitive information to sales, marketing and product groups. Coordinate major quotes and product specifications with sales. MARTIN MARIETTA ELECTRONICS & MISSILES GROUP (1986 to 1990) Orlando, FL Development Engineer: Member of the Research, Development & Technologies Group at the Optical Components Center. Responsible for optical thin film design and fabrication of VIS and IR systems. This includes optical end environmental testing, fabrication, and assembly. Familiar with a variety of film deposition techniques such as PVD, RIPD, CVD and sputtering. Involved in the development of state of the art rain erosion and low observables technology. Developed and constructed BRDF measurement facility and a holographic inspection station for the diamond turning. Education ________________________________________________________________________________ SUNNY at Stony Brook Stony Brook, NY (1978 to 1982) B.S. ENGINEERING CHEMISTRY & BIOCHEMISTRY- Emphasis on physical chemistry and genetic engineering (Recombinant DNA research and micro biology) University of Rochester Rochester, NY (1983 to 1985) M.S. MATERIAL SCIENCE- Emphasis on ceramics and optical materials University of Central Florida Orlando, FL (1986 to 1990) M.S. ELECTRICAL ENGINEERING- uncompleted Courses: Digital circuits, electromagnetic fields, signals & communication, electronic engineering, optics, thin films & technology. University of California Los Angeles, CA (1986) UCLA extension course on optical coating technology given by Phil Baumeister
  • 3. Organizations & Patents _______________________________________________________________________________ At various times member of GaAs MANtech, MRS, UGIM, SPIE, OSA, AVS and IEEE, SWE. ASE, PITCON Patents: Micro-machined component and method of manufacture ,US Pat. 6811714 Issued 11/2/2004 –Freescale Improved interface between a I-III-VI2 material layer and a molybdenum substrate, App. Num. EP20100306519 20101227 App. Date 12/27/2010-Nexis IBM Patent name Patent date Patent number Patent issuing country or region INHIBITION OF TIN OXIDE FORMATION IN LEAD FREE INTERCONNECT FORMATION 2005-05-31 6900142 United States INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 2008-08-12 7410833 United States STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 2007-12-25 7312529 United States INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 2008-10-03 4195886 Japan STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 2010-05-11 7714452 United States INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 2010-04-28 ZL200510060057.1 China METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL CAP STRUCTURE 2011-01-04 7863183 United States METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL CAP STRUCTURE 2011-03-16 ZL200780001812.6 China INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 2011-04-12 7923849 United States INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS 2011-09-27 8026613 United States METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL CAP STRUCTURE 2013-01-25 5186392 Japan Papers: “Finite Amplitude Rotational Surface Tension Instabilities”, Second Annual Mixed Fluids Conference, Casowasco, NY, March 1985. “Green” Process and productivity Improvements in GaAs light emitting dopdes Wafer Fab, Electronics and the environment; May 1995. Optimization of surface Altering processing for GaAs Light emitting diodes, US conference on GaAs Manufacturing TECHnology; May 1995 MAT’s and ISTFA on “Evaluation and Elimination of Forward Snapback defect in GaAs Light Emitting Diodes”, “Green Process and Productivity Improvements in GaAs LED Wafer Fab.” IEEE Electronics and the Environment, Orlando, FL, May 1995. “Excimer laser debridement of necrotic erosions of skin without collateral damage “, Proc. SPIE 8092, 809213 (2011); doi:10.1117/12.889741