1. Sl.No. Aggregate
1 2012 74.00%
2 2008 87.00%
3 2006 92.50%
RESUME
Personal Details:
Name: Ganesh Mallya
E-mail ID: ganesh.mallya1990@gmail.com
Mobile: 919880105084
Linkedin Profile : https://in.linkedin.com/in/ganesh.mallya
Objective:
To apply my progressively updated knowledge in devising the most benefiting solutions which improves the quality of work and add value to the team that I work with and make a big impact to my
organization
Experience:
Experience Summary:
Sankalp Semiconductor Pvt Ltd as Design Engineer since August 2012 .
Sankalp Semiconductor Pvt Ltd as Senior Design Engineer since April 2016.
Total Industry Experience: 4 Years 1 Months
Skill Set:
Operating System: Linux, Windows
Programming & Scripting: Skill, Perl, shell, calibre and pvs rule writing
EDA Tools:
Cadence: Virtuoso 6.1.6 XL, Assura, PVS, Assura QRC, PVS QRC
Mentor Graphics: Calibre,
Areas of Expertise: Area Number of Years
Analog and Mixed Signal Layout 4 years 1 month
Technology Nodes: 28nm, 65nm, 90nm, 130nm, 180nm,16nm finfet
Academics:
Qualification Institute
B.E. in Electronics
And Communication
St Joseph Engineering College
Mangalore
Pre University Certificate MGM College Udupi
SSLC Nehru High School Alevoor Udupi
Project Details:
1
Project / Block Name : Power Management test-chip
Technology: tsmc 28nm
Team Size: 4
Duration: March,2016-April, 2016
Tools Used: Virtuoso 6.1.6 XL, PVS,hercules, Assura
Project Description: Layout design of complete test-chip that includes various IP blocks along with digital and ESD circuits
Responsibilities:
TOP level routing, adding buffers on all control and digital lines, all chip-level verifications, ESD checks of all IP blocks
Challenges/Issues faced :
1.Chip-level density checks- Solutions for maximum density errors created from tools
2.Added buffers on all control and digital signals using skill scripts
3. Schedule and resource utilization challenges to perform all the tasks along with ESD checks/ changes for all internal IP blocks
2

2. Project / Block Name : Power Management IP blocks
Technology: tsmc 28nm
Team Size: 4
Duration: Dec,2015-Feb,2016
Tools Used: Virtuoso 6.1.6 XL, PVS,hercules, Assura
Project Description: Layout design of BGTS block that includes temperature sensor , VBGAP, buffers, digital control, level-shifters and muxout blocks
Responsibilities: Complete responsibility of BGTS block from internal blocks to top-level design
Challenges/Issues faced :
1. Device matching constraints in temperature sensor and VBGAP-Resistor, MOS and BJT matching
2.Shielding of reference signals
3.ESD and latch-up constraints for PAD connected devices and victims during device placement
3
Project / Block Name : Power Management IP blocks
Technology: tsmc 28nm
Team Size: 5
Duration: Aug,2015-November,2015
Tools Used: Virtuoso 6.1.6 XL, PVS,hercules, Assura
Project Description:
Layout design of VBIASP_TOP IP which includes PFETs, fast-loop, resistor divider, bias block and level shifters
Layout design of 0P9 and 1P8 POK Ips which includes comparators, resistor divider, muxout and level-shifters
Responsibilities: Complete responsibility of both IP blocks from internal blocks to top-level design
Challenges/Issues faced :
1. Device matching constraints in fast-loop and resistor divider circuits
2.Meeting low parasitic R and high current value constraints for PFETs
3.ESD and latch-up constraints for PAD connected devices and victims
4
Project / Block Name : MIPI MPHY
Technology: smic 28nm
Team Size: 6
Duration: February 2015 - August 2015
Tools Used: Virtuoso 6.1.6 XL, PVS
Project Description: MPHY layout design consisting of Transistor, Receiver and Common Module IP's
Responsibilities: Complete ownership of common module containing blocks like PLL, Bandgap generation and LDO
Challenges/Issues faced : 1.Schedule management of commun module IP, assigning sub blocks to team mates and taking care of execution and timely review of all the sub blocks
2.Device matching, parasitic matching in PLL ring oscillator working at 5GHz, area optimization, IR drop and EM
5
Project / Block Name : LVDS18 IO LIBRARY DEVELOPMENT
Technology: tsmc 130nm
Team Size: 2
Duration: August 2014 - December 2014
Tools Used: Virtuoso 6.1.6 XL, Calibre
Project Description: Complete LVDS18 IO library development

3. 1
2
2
Responsibilities: 1. Complete ownership of blocks like receiver, ESD cells, Power cells, Corner cell
2. Responsible for complete library verification and delivery
Challenges/Issues faced :
1. Understanding and implementing ESD and Latch up guidelines in RX, power cells and esd cells
2. Area optimization to fit into the given area, mainting minimum parasitic through out the signal path.
3. Taking care of EM and IR for high currents through out the pad ring
6
Project / Block Name : Power management IP blocks- BGR, NMOS and PMOS LDO, Buck DC-DC converter
Technology: tsmc 65nm
Team Size: 2
Duration: April 2013- October 2013
Tools Used: Virtuoso 6.1.6 XL, Calibre
Project Description: Layout design of BGR, PMOS and NMOS LDOs( 150 and 300mA) which includes resistor divider, error amplifier and VI ref circuits
Responsibilities: Complete ownership of blocks above mentioned from internal blocks to top-level design
Challenges/Issues faced :
1. Device matching constraints in BGR, error amplifiers, VI ref block
2. Shielding of reference signals
3. Meeting low resistance and high current value constraints for LDO blocks
Automations :
1.Worked on shell, skill, perl and calibre rule writing
2. Written several bindkeys and few layout tasks in skill
3.Written perl scripts for text processing tasks observed in release time
3.Written batch mode verification scripts in shell programming- Generating GDS, netlist, running checks
4. Applied calibre rule writing to perform few useful layout checks
Trainings Undergone :
1.Worked on memory block for full chip Blood Pressure Monitoring System layout
2.Worked on VCO block for PLL layout
3.Worked on PIPE line ADC and current steering DACs
3.Calibre rule writing
4. Special training course on ESD and Latch-up conducted from ESD experts
5. Worked on amplifier blocks in 16nm finfet
Achievements and Awards:
Awarded for execution, quality and on-time delivery in mulitple quarters at Sankalp Semiconductor Pvt Ltd
Received team awards for multiple projects at Sankalp Semiconductor Pvt Ltd
Received "Training Champion" award for analog layout training for newly joined folks
Personal Strengths :
1. Good at execution and meeting on-time goals
2. Penchant for learning new things, exploring and trying out different options
3. Self motivated and goal oriented

4. Personal Details :
DOB : 15th March 1990
Address : H.No.37, Beside Rambapuri Samudaya bhavana, Vidhyavana, Vidhyanagar, Hubli-580031
Marital Status : Single
Nationality : Indian
Languages : Kannada, Hindi and English
I hereby declare that all the information furnished is true to the best of knowledge and belief
Ganesh Mallya
Date:15 Aug 2016 Place :HUBLI