1. MINI BLACK JACK

2. Introduction Logical Model Simulation Synthesis References Contribution Contents

3. This is nothing but an implementation of Black Jack. The input signal is nothing but a start/stop key. The output is a random count displayed on Seven Segment Display and sum in binary form indicated by output LED’s. This program was written using a VHDL code and downloaded on a Xilinx FPGA.This is a game which we play in the casino known as 21 but this is a mini version also known as 12. Introduction

4. Logical Model Mini Black jack Start/Stop SSD Clock Sum Output

5. The mini black jack uses a fsm in a random order,interfacing the program with SSD. The user starts the game using start and stop button, the number is displayed on the SSD and is summed with the previous number and displayed in the binary form on the LEDs. If the sum is 10,11or12 then the user wins and will be indicated by the output. Working

6. The Mini Black Jack program was simulated using the Model Sim v5.1 simulator from ModelTech. The simulation was found to be an accurate representation of what we wanted the Black Jack Game to do. Simulation

7. The code was written and checked for syntactical errors. Those found were removed. The code was tested by giving a set of inputs on the test bench. The results were as expected. The code was loaded on the FPGA and on running it we realized there was a minor error that the outputs were not resetting upon making the inputs low. The necessary changes were made in the code and it was again loaded on the FPGA. The results this time were as expected. Synthesis

8. VolneiA.Pedroni,Circuit Design With VHDL,MIT Press,London www.xilinx.com References