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MAC UNIT USING DIFFERENT MULTIPLIERS

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Bhamidipati Gayatri

IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES FOR CONVOLUTION APPLICATION IN SIGNAL PROCESSING

TechnologieBusiness
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IMPLEMENTATION OF FAST MULTIPLIER ARCHITECTURES FOR CONVOLUTION APPLICATION IN SIGNAL PROCESSING K.SUSHMA(709212142027) B.GAYATRI(709212142008)
INTRODUCTION  Convolution is the fundamental and important operation in Signal processing  Multiply-accumulate operation is widely used in Convolution  Computes the product of two numbers and adds that product to an accumulator  Consists of a multiplier followed by an accumulator that contains the sum of the previous consecutive products
BLOCK DIAGRAM OF MAC UNIT
 Different multipliers like a)Vedic multiplier b)Column bypass multiplier c)Multiplier using different Compressors can be used
VEDIC MULTIPLIER
VEDIC MATHEMATICS  Ancient technique which simplifies multiplication, division, squaring and cubing of a number etc .  Unique technique of calculations based on simple principles and rules.  Consists of sixteen mathematical sutras and Upa sutras.
URDHVA- TRIYAGBHYAM  One of the sixteen Vedic sutras.  Urdhva means vertical and Triyagbhyam means crosswise.
LINE DIAGRAM FOR MULTIPLICATION OF TWO- 4 BIT NUMBERS  STEP 1:  STEP 2:  STEP 3:
 STEP 4:  STEP5:  STEP 6:  STEP 7:
CIRCUIT DIAGRAM OF 4-BIT VEDIC MULTIPLIER
BLOCK DIAGRAM OF 8X8 VEDIC MULTIPLIER
SIMULATED WAVE FORM OF 16-BIT VEDIC MULTIPLIER USING XILINX 13.1i
SIMULATED WAVEFORM OF 16-BIT MAC
4-BIT VEDIC MULTIPLIER MASK LAYOUT
SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
COLUMN BYPASS MULTIPLIER
COLUMN BYPASS MULTIPLIER  If any bit of the multiplicand is zero, then the corresponding partial product will be zero  Therefore, the column of adders need not to be activated  If aj=0 then the corresponding operations in a column can be disabled
CIRCUIT DIAGRAM OF 4X4 COLUMN BYPASS MULTIPLIER
BLOCK DIAGRAM OF MODIFIED FULL ADDER CELL  Full-Adder  Tri-state buffer  Mux 2-1
SIMULATED WAVE FORM OF 16-BIT COLUMN BYPASS MULTIPLIER
SIMULATED WAVEFORM OF 16-BIT MAC
4-BIT COLUMN BYPASS MULTIPLIER MASK LAYOUT
SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
MULTIPLIER USING DIFFERENT COMPRESSORS AND ADDERS
BLOCK DIAGRAM OF MULTIPLIER USING COMPRESSOR AND ADDERS
BLOCK DIAGRAM OF DIFFERENT COMPRESSORS
ARCHITECTURE OF 8X8 MULTIPLIER USING COMPRESSORS
SIMULATED WAVE FORM OF 16-BIT MULTIPLIER USING COMPRESSORS
SIMULATED WAVEFORM OF 16-BIT MAC
4-BIT MULTIPLIER USING COMPRESSOR MASK LAYOUT
SIMULATED OUTPUT WAVEFORM USING MICROWIND LAYOUT EDITOR
SYNTHESIS RESULTS ON XILINX 13.1I Multiplier 16*16 Number of LUT’s Vedic 726 Column Bypass 716 Compressors 729 Multiplier Type Vedic Compressors Column Bypass Vendor Xilinx Xilinx Xilinx Device and Family Spartan3E Spartan3E Spartan3E Estimate Delay 48.258 ns 41.795 ns 46.105 ns Power 81mW 81mW 41mW
APPLICATIONS  Convolution  DSP processor  FFT
THANK YOU

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