Learn more about the Nios II embedded processor, its CPU architecture, its build tools, and embedded Linux for the Nios II processor.

1. © 2010 Altera Corporation—Public
Nios II Embedded Processor

2. © 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
 Overview
 CPU architecture
 Multiprocessor designs
 Nios II software build tools
 Embedded Linux for Nios II processor
2
Agenda

3. © 2010 Altera Corporation—Public
Overview

4. © 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.
and Altera marks in and outside the U.S.
4
Nios II Processor Overview
FPGA
Your Design Here
TCM
D-MEM
TCM
I-MEM
CUSTOM
INSTR IF
I$ D$
INT
CNTRL
JTAG
DEBUG
HW
BP
I & D
TRCE
TRCE
PORT
Debug
EXP
CNTRL
MMU MPU
* Dhrystones 2.1 benchmark
 Family of configurable
32-bit embedded processors
 Performance over 300 MIPS*
(Nios II/f core with Stratix series FPGAs)
 Core cost as low as 25 cents in logic
(Nios II/e core with Cyclone III FPGAs)

5. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Custom fit to users’ application
 Fill gaps inherent in off-the-shelf devices
 Allow users to add their “secret sauce”
 Protect design from obsolescence
 Work with all Altera FPGA devices
 Perpetual-use license protects software
 Scale performance
 Multi-CPU
 Custom instructions
 Hardware accelerators
 Deliver the right product at the right
price in the shortest time
 From concept to system in minutes
5
Why Developers Choose Nios II Processors
DesignWare
Star IP

6. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Over 30,000 licensees worldwide
 Used by top 20 OEMs
 Used by developers in all Altera markets
 Industry’s #1 soft core CPU (source: Gartner Dataquest)
 Vibrant Altera Forum community (over 30,000 registered users)
6
Nios II Processor Adoption

7. © 2010 Altera Corporation—Public
CPU Architecture

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and Altera marks in and outside the U.S.
Processor Core Variations
8
Nios II/f Fast
Core
Nios II/s
Standard Core
Nios II/e
Economy Core
Pipeline 6 stage 5 stage None
Hardware Multiplier
and Barrel Shifter
1 cycle 3 cycle Emulated
in software
Branch Prediction Dynamic Static None
Instruction Cache Configurable Configurable None
Data Cache Configurable None None
Logic Elements
(LEs)
1,800 without
MMU
3,200 with MMU
1,200 600
Custom
Instructions
Up to 256
DO-254 Certifiable Core Based on
Nios II/f Variation (Without MMU)

9. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Nios II Processor Performance (MIPS*)
Device Family Nios II/f Core
Standard-cell ASIC (~90 nm) >500
Stratix IV 340
Stratix III 340
Stratix II 250
HardCopy IV 345
HardCopy III 260
Hardcopy II 230
Arria II GX 283
Cyclone IV GX 186
Cyclone III LS 158
Cyclone III 195
Cyclone II 145
9
* Dhrystones 2.1 benchmark

10. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
10
Nios II Processor Configuration
Program
Controller
and
Address
Generation
clock
reset
Status and
Control
Registers
Instruction
Master
Port
Instruction
Cache
Data
Cache
Data
Master
Port
General
Purpose
Registers
Nios II Processor Core
Optional Configurable
Debug OptionsFixed
Tightly
Coupled
I-Memory
Tightly
Coupled
D-Memory
irq[31..0]
Arithmetic
Logic Unit
Interrupt
Controller
Exception
Controller
Trace
Memory
Instructionand
DataTrace
High-speed
Connection
to Trace Pod
Trace Port
Hardware-
assisted
Debug Module
JTAG Interface
to Software
Debugger
Hardware
Breakpoints
Custom
Instruction
Logic
Custom
I/O Signals
MMU
MPU

11. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Configurable instruction and data*
 Direct mapped
 512 bytes – 64 KB
 One to four tightly coupled memory interface ports
11
Nios II Caches
* Data cache not currently included in Nios II DO-
254 certifiable version

12. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
12
Nios II Vector Interrupt Controller
 Real time for fast, deterministic response
to real-world events
 Example: sensors, actuators, etc.
 External interrupt controller interface
 Allows user to connect custom interrupt
controller to CPU or use VIC from Altera
 Features
 Interrupt service response latency – 5 times
faster response (< 20 clock cycles)
 Non-maskable interrupt (NMI) – guaranteed
response to high priority interrupt
 Daisy-chain interrupt sources – 32
interrupts per VIC, daisy chain for more
 HAL driver support – provided driver API for
ease of use, user-defined ISR also possible
r0..31r0..31r0..31r0..31r0..31r0..31r0..31
Instruction
Master
Data
Master
Fetch
Decode
Execute
Memory
Align
Writeback
I$ D$
I
TCM
D
TCM
Int
Cont
Control
Registers
DebugJTAG
Avalon Avalon
W/no busy
Avalon
W/no busy
Avalon
EICIRQ Vector
Valid
Avalon
Streaming
Reg Sel
r0..31r0..31r0..31r0..31r0..31r0..31r0..31

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and Altera marks in and outside the U.S.
 Debug unit configuration
 JTAG
 Software download
 Software breakpoints
 Hardware breakpoints
 Data triggers
 Instruction/data trace
 On chip
 Off chip
13
Configurable Software Debug Unit

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and Altera marks in and outside the U.S.
14
Building an SOPC Builder System
DMA
Read
_ Master
Write
_Master
Control
port
slave
Nios II
Processor
Data
_Master
Instruction
_Master
ETHERNET_MAC
DMA
_Master
Igor_the
_Slave
SDRAM
Onchip_
Memory
UART TIMER GPIO
SOPC Builder automatically generates
system interconnect fabric

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and Altera marks in and outside the U.S.
SOPC Builder: Slave-Side Arbitration
15
Master 1
Slave 2 Slave 3
Master 2
Master
Slave
Master 3
Slave 4
System Interconnect Fabric
Arbiter Arbiter
Slave 1
System Interconnect Fabric System Interconnect Fabric
Slave-Side Arbitration Increases
System Performance

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and Altera marks in and outside the U.S.
 Avalon® Memory-Mapped (Avalon-MM) interface
 Address-based switch fabric
 Avalon Streaming (Avalon-ST) interface
 Enables systems with streaming unidirectional flow of data,
including multiplexed streams, packets, and digital signal
processing (DSP) data
16
Avalon Memory-Mapped and Streaming
Interface

17. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Component Editor
 Imports HDL files
 Assigns signals, ports, and
parameters
 Assigns software drivers
 Packaged as SOPC Builder
components
 Facilitates design reuse
17
Adding Your Own Components

18. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Three Ways to Scale Performance
18
External
CPU or
DSP
Multiprocessor
System
PCITM
FPGA
CPU
CPU
CPU
CPU
Custom
Instructions
FPGA
Hardware
Accelerators
FPGA CPU
Hardware
Accelerator
Hardware
Accelerator
CPU
Custom
Instructions
 Adds processors
(internal and external)
 Accelerate individual
CPU performance
(add application-
specific instructions)
 Accelerate data
transformation
algorithms with
application-specific
hardware

19. © 2010 Altera Corporation—Public
Multiprocessor Designs

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and Altera marks in and outside the U.S.
20
Common Multiprocessor Designs
Asymmetric
Multi-core
Co-processor /
Companion Chip
Multi-channel
Processing

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and Altera marks in and outside the U.S.
Custom Instructions
 Extend CPU performance
 CPU fetches data and stores results
 Ideal for math and logical operations
(for example: floating point and bit manipulation)
 Hardware is much faster than software
21
Example: CRC 64-KB buffer
0
40
60
80
100
120
Iterations/Second
Software
Only
Custom
Instruction
20
27X
Faster Out<<
>>
&
Custom
Logic
+-
A
B
Nios II Embedded Processor

22. © 2010 Altera Corporation—Public
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Hardware Accelerators
 Concurrent data co-processing
 CPU starts and stops the co-processor
 Co-processor fetches data and stores results
 CPU runs application code concurrently
 Ideal for block data operations
22
Example: CRC 64-KB buffer
CRC
Co-processor
Program
Memory
CPU
Data
Memory
Arbiter
Data
Memory
Arbiter
Co-processor
0
5,000
1,000
1,500
2,000
2,500
Iterations/Second
Software
Only
Custom
Instruction
530X
Faster

23. © 2010 Altera Corporation—Public
Nios II Software Build Tools

24. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Single Developer Software Project
Productivity = Ease of Use
Getting Started Quickly
Choose a template, point to system file, and build
Automation in Build
Automatically builds system library to include drivers,
newlib C, Hardware Abstraction Language (HAL) files, and
software packages
One-stop Shop
Source editor, compiler, debugger, profiler, flash
programmer, software templates, etc.
Easy-to-make Settings
GUI for common software settings, linker regions, STDIN,
and STDOUT
24
User Application
Operating System or HAL
DriverDriver DriverDriver
IPIP IPIP
File
System
Network
Stack
Graphics
Library
Other
Software
Packages
Driver
IP
Just
Add
Code
Automation

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and Altera marks in and outside the U.S.
Multi-Developer Software Project
Productivity = Full Control over Build
Sophisticated Build Management
Makefile-based and scriptable for overnight build
Revision Control Centric
Support for relative paths, build settings, and versioning device
drivers
“Power” User Settings
Fine control over build options, choice of device drivers, software
packages, and linker regions
25
User Application
Operating System or HAL
DriverDriver DriverDriver
IPIP IPIP
File
System
Network
Stack
Graphics
Library
Other
Software
Packages
Driver
IP
BuildManagement

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and Altera marks in and outside the U.S.
26
The Solution: Nios II Software Build Tools
Nios II Software Build Tools
 Application makefile
 Board support package (BSP) makefile
 Library makefile
 Software project settings
Plug-ins to Eclipse-based IDENios II Command Shell: Commands and Scripts

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and Altera marks in and outside the U.S.
Project Management
27
Features:
• Project manager
• Editor and compiler
• Debugger
• Flash programmer
Software
Templates
• Easy-to-use
examples
• Users may
add their own
templates
Integrated Software Project Management
Project
Management
• Project
navigation
• Source files
•
• System library
customized to
hardware
• Easy
configuration
Software
Components

28. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Editor and Compiler
28
Integrated Editor and Software
Toolchain Functionality
Project
Management
• Basic editing
capabilities
• C/C++ syntax
highlighting
•Comprehensive
search
• Help feature
Source Editor
• Project
navigation
• Source files
• Compiler
based on GNU
toolchain
• Command-line
operation
possible
Compiler
Features:
• Project manager
• Editor and compiler
• Debugger
• Flash programmer

29. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Debugger
29
Basic Debug
Debug targets:
• Hardware (JTAG)
• Instruction set
simulator
• Logic simulator
(ModelSim®)
Debug scope:
• Hardware/software
breakpoints
• Hardware data triggers
• Watchpoints
• Instruction trace
Debug Scope
Integrated, Broad Capability Debug
• Breakpoints
• Code position
Source View
• Run controls
• Stack view
• Active debug
sessions
• Variables
• Registers
• Signals
Memory View
Features:
• Project manager
• Editor and compiler
• Debugger
• Flash programmer

30. © 2010 Altera Corporation—Public
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Flash Programmer
30
Programming
Targets
• Manage and
program flash
devices
• Utilizes JTAG
download
cable
Functionality
Memory Supported
• CFI-compliant flash
• Altera EPCS devices
Integrated Flash Programmer Utility
• FPGA
configuration
• System
firmware
Features:
• Project manager
• Editor and compiler
• Debugger
• Flash programmer

31. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Nios II Software Build Flow
31
BSP
Generation
• Full control
over all build
options
• Customized
scripting using
command lines
or Tcl script
• Better revision
control and
BSP handoff
Functionality
Debug
• Uses Nios II
IDE Debugger
• Integrated board
level debug
For Full Control over Build Options and Scripting
Features:
• Makefile-based
• Nios IDE debugger
• BSP generation
• Tcl-based scripting
• Tools for
creating and
managing BSP

32. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
32
Nios II HAL
Nios II Processor System Hardware
Device
Driver
Device
Driver
Device
Driver…
 Provides run-time services and device drivers which interface to the hardware
 Allows you to change your hardware without having to change your software code
 Creates a matching custom software BSP automatically when hardware is generated
_exit()
close()
closedir()
fstat()
getpid()
gettimeofday()
ioctl()
isatty()
kill()
lseek()
open()
opendir
read()
readdir()
rewinddir()
sbrk()
settimeofday()
stat()
usleep()
wait()
write()
HAL API
HAL API
Shared Library
User Program

33. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Nios II Embedded Design Suite
3333
Integrated Software
Development:
Manage, Build, Debug
Command Line-
based Software
Build Flow
HAL API
Peripheral Drivers
and Run-time
Software Library
Embedded
Design Suite
GNU Tools
Debugger, C/C++
Compiler

34. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
Nios II Embedded Design Suite
3434
Real-time Operating
System from Micrium
(DO-178B Certifiable)*
Advanced Debugging
Tools from Lauterbach*
Commercial-grade
Network Stack from
Interniche*
* Full evaluation included in kit and web download – license sold separately
Embedded
Design Suite

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and Altera marks in and outside the U.S.
ERIKA & RT-Druid
Timesys LinuxLink
Open Source
Linux
uCLinux
Partner Operating System Support
35

36. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Altera Forum
 Over 30,000 registered users
 Thousands of searchable topics
 Hardware and intellectual
property (IP)
 Software development
 Operating system
 Altera Wiki
 User contributions
 IP and reference designs
 Software
 Operating systems (Linux, uCLinux)
 Documentation
36
Vibrant User Community
www.alterawiki.com
www.alteraforum.com

37. © 2010 Altera Corporation—Public
Embedded Linux for Nios II
Processor

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and Altera marks in and outside the U.S.
Linux Solution Space
38
Embedded Linux
System Components
Supplier/Support
Altera CodeSourcery
Open
Source
Timesys SLS
Software
Packages
Kernel
Drivers
Toolchain
Hardware
Reference design
IP cores
Design software

39. © 2010 Altera Corporation—Public
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and Altera marks in and outside the U.S.
 Simple license/subscription business model
 Royalty-free, no redistribution language
 Discounts for larger quantities and longer terms
 Hosted computing model for ease of use
 Web-based version of LinuxLink for quick,
easy creations of custom starting points
 Desktop toolset for full life cycle support
 Same framework, similar features
 Worldwide expert technical support
 Included in license fee
39
LinuxLink by Timesys for the Nios II
Processor

40. © 2010 Altera Corporation—Public
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 Three versions
40
CodeSourcery G++ for the Nios II
Processor www.codesourcery.com > Partners > Altera Nios II

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and Altera marks in and outside the U.S.
 Development kit choices
 Embedded Systems Development Kit,
Cyclone III Edition
 Stratix IV GX Development Kit
 Nios II Embedded Evaluation Kit (NEEK),
Cyclone III Edition
 Hardware reference designs
 EP3C120 (Altera web page)
 EP4SGX230 (Altera web page)
 NEEK (Nios Wiki)
41
Linux Development PlatformsDevelopment/Prototype
Demo/Proof of Concept
EP3C120
EP4SGX230
NEEK

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CPU Platform
System Functions
Nios II/f
(MMU and
TCM)
JTAG
Debug
8-KB
I-Cache
8-KB
D-Cache
PLL/
System
Clock
System ID
Memory Interface
1-MB
SSRAM
32-MB
DDR
SDRAM
16-MB
SD Card
Communications Interface
JTAG
UART
FIFO
UART
TSE MAC
with TX and
RX DMA
EEPROM PIO
(MAC
Address)
16-MB
Flash
Tristate
Bridge
System
Timer
High-
resolution
Timer
On-chip
RAM
System Peripherals
LCD/
Touch
Panel
Push
Button
PIO
VGA
Interface
Video
Pipeline
42
NEEK Linux Design Example

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Debug I and D TCM
8K I and D Cache
Nios II/f Core
with MMU
Timer
High-resolution
Timer
FIFO
UART
Sys ID
JTAG
UART
Button PIO
LCD PIO
(I2C)
Touch
Panel SPI
Touch
Panel PIO
Video PLL
SD Card
On-chip
RAM
(DMA Descriptors)
Tristate
Bridge
SSRAM
Interface
(Image Buffer)
Flash
Interface
DDR
Interface
Frame
Reader
FIFO
Color
Plane
Sequencer
Video Out
(VGA)
Clipper
Video Out
(LCD)
EEPROM
PIO
SG-DMA
(TX)
SG-DMA
(RX)
Legend
100 MHz
50 MHz
120 MHz
Streaming Interface
TSE MAC
NEEK Linux Design Example Block Diagram
43

44. © 2010 Altera Corporation—Public
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 Slideshow running on NEEK’s LCD panel and VGA port
44
Slideshow Application (Pictures Stored on SD Card)
Linux Kernel
FBUART VGATouch SD
Nios II with MMU
LCD
FIFO
UART
Touch
Panel
DDR SD Card
Cross Tools/Device Utilities/Factory
Quartus Design Software
Touch
Calibration
BusyBox DirectFBlibjpeg
File System
Utility
HardwareSoftware
Design Example: Software Stack

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High
Performance
 Multi-processor
 Hardware acceleration
 Custom instructions
 Vector interrupt controller
 Linux, eCos, uC-OS, Thread X OS
 USB, NAND flash, mobile DDR IP
 Lauterbach trace, network stack, etc.
Greatest
Flexibility
Powerful
Design Tools
Largest
Ecosystem
 Configurable processor, peripherals
 MMU or MPU
 FPGA, HardCopy or Synopsys ASIC
 DO-254 certifiable
 Complete set of SW development tools
 Industry-leading embedded partners
 SOPC Builder system development tool
Nios II Processor - Leading the Industry

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